1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_PERIPH_H 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_PERIPH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Peripherals required for pinmux configuration. List will 13*4882a593Smuzhiyun * grow with support for more devices getting added. 14*4882a593Smuzhiyun * Numbering based on interrupt table. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum periph_id { 18*4882a593Smuzhiyun UART_GPIOC_30_31 = 0, 19*4882a593Smuzhiyun UART_GPIOB_16_17, 20*4882a593Smuzhiyun ETH_GPIOB_10_31_C_0_4, 21*4882a593Smuzhiyun QSPI_CS_CLK_PAD, 22*4882a593Smuzhiyun PERIPH_ID_I2C0, 23*4882a593Smuzhiyun PERIPH_ID_I2C1, 24*4882a593Smuzhiyun PERIPH_ID_I2C2, 25*4882a593Smuzhiyun PERIPH_ID_I2C3, 26*4882a593Smuzhiyun PERIPH_ID_I2C4, 27*4882a593Smuzhiyun PERIPH_ID_I2C5, 28*4882a593Smuzhiyun PERIPH_ID_I2C6, 29*4882a593Smuzhiyun PERIPH_ID_I2C7, 30*4882a593Smuzhiyun PERIPH_ID_SPI0, 31*4882a593Smuzhiyun PERIPH_ID_SPI1, 32*4882a593Smuzhiyun PERIPH_ID_SPI2, 33*4882a593Smuzhiyun PERIPH_ID_SDMMC0, 34*4882a593Smuzhiyun PERIPH_ID_SDMMC1, 35*4882a593Smuzhiyun PERIPH_ID_SDMMC2, 36*4882a593Smuzhiyun PERIPH_ID_SDMMC3, 37*4882a593Smuzhiyun PERIPH_ID_I2S1, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum periph_clock { 41*4882a593Smuzhiyun UART_CLOCK_CFG = 0, 42*4882a593Smuzhiyun ETH_CLOCK_CFG, 43*4882a593Smuzhiyun QSPI_CLOCK_CFG, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_PERIPH_H */ 47