1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _STV0991_CREG_H 9*4882a593Smuzhiyun #define _STV0991_CREG_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct stv0991_creg { 12*4882a593Smuzhiyun u32 version; /* offset 0x0 */ 13*4882a593Smuzhiyun u32 hdpctl; /* offset 0x4 */ 14*4882a593Smuzhiyun u32 hdpval; /* offset 0x8 */ 15*4882a593Smuzhiyun u32 hdpgposet; /* offset 0xc */ 16*4882a593Smuzhiyun u32 hdpgpoclr; /* offset 0x10 */ 17*4882a593Smuzhiyun u32 hdpgpoval; /* offset 0x14 */ 18*4882a593Smuzhiyun u32 stm_mux; /* offset 0x18 */ 19*4882a593Smuzhiyun u32 sysctrl_1; /* offset 0x1c */ 20*4882a593Smuzhiyun u32 sysctrl_2; /* offset 0x20 */ 21*4882a593Smuzhiyun u32 sysctrl_3; /* offset 0x24 */ 22*4882a593Smuzhiyun u32 sysctrl_4; /* offset 0x28 */ 23*4882a593Smuzhiyun u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ 24*4882a593Smuzhiyun u32 mux1; /* offset 0x100 */ 25*4882a593Smuzhiyun u32 mux2; /* offset 0x104 */ 26*4882a593Smuzhiyun u32 mux3; /* offset 0x108 */ 27*4882a593Smuzhiyun u32 mux4; /* offset 0x10c */ 28*4882a593Smuzhiyun u32 mux5; /* offset 0x110 */ 29*4882a593Smuzhiyun u32 mux6; /* offset 0x114 */ 30*4882a593Smuzhiyun u32 mux7; /* offset 0x118 */ 31*4882a593Smuzhiyun u32 mux8; /* offset 0x11c */ 32*4882a593Smuzhiyun u32 mux9; /* offset 0x120 */ 33*4882a593Smuzhiyun u32 mux10; /* offset 0x124 */ 34*4882a593Smuzhiyun u32 mux11; /* offset 0x128 */ 35*4882a593Smuzhiyun u32 mux12; /* offset 0x12c */ 36*4882a593Smuzhiyun u32 mux13; /* offset 0x130 */ 37*4882a593Smuzhiyun u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ 38*4882a593Smuzhiyun u32 cfg_pad1; /* offset 0x200 */ 39*4882a593Smuzhiyun u32 cfg_pad2; /* offset 0x204 */ 40*4882a593Smuzhiyun u32 cfg_pad3; /* offset 0x208 */ 41*4882a593Smuzhiyun u32 cfg_pad4; /* offset 0x20c */ 42*4882a593Smuzhiyun u32 cfg_pad5; /* offset 0x210 */ 43*4882a593Smuzhiyun u32 cfg_pad6; /* offset 0x214 */ 44*4882a593Smuzhiyun u32 cfg_pad7; /* offset 0x218 */ 45*4882a593Smuzhiyun u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ 46*4882a593Smuzhiyun u32 vdd_pad1; /* offset 0x300 */ 47*4882a593Smuzhiyun u32 vdd_pad2; /* offset 0x304 */ 48*4882a593Smuzhiyun u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ 49*4882a593Smuzhiyun u32 vdd_comp1; /* offset 0x400 */ 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* CREG MUX 13 register */ 53*4882a593Smuzhiyun #define FLASH_CS_NC_SHIFT 4 54*4882a593Smuzhiyun #define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) 55*4882a593Smuzhiyun #define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define FLASH_CLK_SHIFT 0 58*4882a593Smuzhiyun #define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) 59*4882a593Smuzhiyun #define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* CREG MUX 12 register */ 62*4882a593Smuzhiyun #define GPIOC_30_MUX_SHIFT 24 63*4882a593Smuzhiyun #define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) 64*4882a593Smuzhiyun #define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define GPIOC_31_MUX_SHIFT 28 67*4882a593Smuzhiyun #define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) 68*4882a593Smuzhiyun #define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* CREG MUX 7 register */ 71*4882a593Smuzhiyun #define GPIOB_16_MUX_SHIFT 0 72*4882a593Smuzhiyun #define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) 73*4882a593Smuzhiyun #define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define GPIOB_17_MUX_SHIFT 4 76*4882a593Smuzhiyun #define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) 77*4882a593Smuzhiyun #define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* CREG CFG_PAD6 register */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define GPIOC_31_MODE_SHIFT 30 82*4882a593Smuzhiyun #define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) 83*4882a593Smuzhiyun #define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) 84*4882a593Smuzhiyun #define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define GPIOC_30_MODE_SHIFT 28 87*4882a593Smuzhiyun #define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) 88*4882a593Smuzhiyun #define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) 89*4882a593Smuzhiyun #define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* CREG Ethernet pad config */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define VDD_ETH_PS_1V8 0 94*4882a593Smuzhiyun #define VDD_ETH_PS_2V5 2 95*4882a593Smuzhiyun #define VDD_ETH_PS_3V3 3 96*4882a593Smuzhiyun #define VDD_ETH_PS_MASK 0x3 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define VDD_ETH_PS_SHIFT 12 99*4882a593Smuzhiyun #define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define VDD_ETH_M_PS_SHIFT 28 102*4882a593Smuzhiyun #define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif 105