1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_HARDWARE_H 9*4882a593Smuzhiyun #define _ASM_ARCH_HARDWARE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* STV0991 */ 12*4882a593Smuzhiyun #define SRAM0_BASE_ADDR 0x00000000UL 13*4882a593Smuzhiyun #define SRAM1_BASE_ADDR 0x00068000UL 14*4882a593Smuzhiyun #define SRAM2_BASE_ADDR 0x000D0000UL 15*4882a593Smuzhiyun #define SRAM3_BASE_ADDR 0x00138000UL 16*4882a593Smuzhiyun #define CFS_SRAM0_BASE_ADDR 0x00198000UL 17*4882a593Smuzhiyun #define CFS_SRAM1_BASE_ADDR 0x001B8000UL 18*4882a593Smuzhiyun #define FAST_SRAM_BASE_ADDR 0x001D8000UL 19*4882a593Smuzhiyun #define FLASH_BASE_ADDR 0x40000000UL 20*4882a593Smuzhiyun #define PL310_BASE_ADDR 0x70000000UL 21*4882a593Smuzhiyun #define HSAXIM_BASE_ADDR 0x70100000UL 22*4882a593Smuzhiyun #define IMGSS_BASE_ADDR 0x70200000UL 23*4882a593Smuzhiyun #define ADC_BASE_ADDR 0x80000000UL 24*4882a593Smuzhiyun #define GPIOA_BASE_ADDR 0x80001000UL 25*4882a593Smuzhiyun #define GPIOB_BASE_ADDR 0x80002000UL 26*4882a593Smuzhiyun #define GPIOC_BASE_ADDR 0x80003000UL 27*4882a593Smuzhiyun #define HDM_BASE_ADDR 0x80004000UL 28*4882a593Smuzhiyun #define THSENS_BASE_ADDR 0x80200000UL 29*4882a593Smuzhiyun #define GPTIMER2_BASE_ADDR 0x80201000UL 30*4882a593Smuzhiyun #define GPTIMER1_BASE_ADDR 0x80202000UL 31*4882a593Smuzhiyun #define QSPI_BASE_ADDR 0x80203000UL 32*4882a593Smuzhiyun #define CGU_BASE_ADDR 0x80204000UL 33*4882a593Smuzhiyun #define CREG_BASE_ADDR 0x80205000UL 34*4882a593Smuzhiyun #define PEC_BASE_ADDR 0x80206000UL 35*4882a593Smuzhiyun #define WDRU_BASE_ADDR 0x80207000UL 36*4882a593Smuzhiyun #define BSEC_BASE_ADDR 0x80208000UL 37*4882a593Smuzhiyun #define DAP_ROM_BASE_ADDR 0x80210000UL 38*4882a593Smuzhiyun #define SOC_CTI_BASE_ADDR 0x80211000UL 39*4882a593Smuzhiyun #define TPIU_BASE_ADDR 0x80212000UL 40*4882a593Smuzhiyun #define TMC_ETF_BASE_ADDR 0x80213000UL 41*4882a593Smuzhiyun #define R4_ETM_BASE_ADDR 0x80214000UL 42*4882a593Smuzhiyun #define R4_CTI_BASE_ADDR 0x80215000UL 43*4882a593Smuzhiyun #define R4_DBG_BASE_ADDR 0x80216000UL 44*4882a593Smuzhiyun #define GMAC_BASE_ADDR 0x80300000UL 45*4882a593Smuzhiyun #define RNSS_BASE_ADDR 0x80302000UL 46*4882a593Smuzhiyun #define CRYP_BASE_ADDR 0x80303000UL 47*4882a593Smuzhiyun #define HASH_BASE_ADDR 0x80304000UL 48*4882a593Smuzhiyun #define GPDMA_BASE_ADDR 0x80305000UL 49*4882a593Smuzhiyun #define ISA_BASE_ADDR 0x8032A000UL 50*4882a593Smuzhiyun #define HCI_BASE_ADDR 0x80400000UL 51*4882a593Smuzhiyun #define I2C1_BASE_ADDR 0x80401000UL 52*4882a593Smuzhiyun #define I2C2_BASE_ADDR 0x80402000UL 53*4882a593Smuzhiyun #define SAI_BASE_ADDR 0x80403000UL 54*4882a593Smuzhiyun #define USI_BASE_ADDR 0x80404000UL 55*4882a593Smuzhiyun #define SPI1_BASE_ADDR 0x80405000UL 56*4882a593Smuzhiyun #define UART_BASE_ADDR 0x80406000UL 57*4882a593Smuzhiyun #define SPI2_BASE_ADDR 0x80500000UL 58*4882a593Smuzhiyun #define CAN_BASE_ADDR 0x80501000UL 59*4882a593Smuzhiyun #define USART1_BASE_ADDR 0x80502000UL 60*4882a593Smuzhiyun #define USART2_BASE_ADDR 0x80503000UL 61*4882a593Smuzhiyun #define USART3_BASE_ADDR 0x80504000UL 62*4882a593Smuzhiyun #define USART4_BASE_ADDR 0x80505000UL 63*4882a593Smuzhiyun #define USART5_BASE_ADDR 0x80506000UL 64*4882a593Smuzhiyun #define USART6_BASE_ADDR 0x80507000UL 65*4882a593Smuzhiyun #define SDI2_BASE_ADDR 0x80600000UL 66*4882a593Smuzhiyun #define SDI1_BASE_ADDR 0x80601000UL 67*4882a593Smuzhiyun #define VICA_BASE_ADDR 0x81000000UL 68*4882a593Smuzhiyun #define VICB_BASE_ADDR 0x81001000UL 69*4882a593Smuzhiyun #define STM_CHANNELS_BASE_ADDR 0x81100000UL 70*4882a593Smuzhiyun #define STM_BASE_ADDR 0x81110000UL 71*4882a593Smuzhiyun #define SROM_BASE_ADDR 0xFFFF0000UL 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* _ASM_ARCH_HARDWARE_H */ 74