1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _STM32_GPT_H 9*4882a593Smuzhiyun #define _STM32_GPT_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch/stm32.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct gpt_regs { 14*4882a593Smuzhiyun u32 cr1; 15*4882a593Smuzhiyun u32 cr2; 16*4882a593Smuzhiyun u32 smcr; 17*4882a593Smuzhiyun u32 dier; 18*4882a593Smuzhiyun u32 sr; 19*4882a593Smuzhiyun u32 egr; 20*4882a593Smuzhiyun u32 ccmr1; 21*4882a593Smuzhiyun u32 ccmr2; 22*4882a593Smuzhiyun u32 ccer; 23*4882a593Smuzhiyun u32 cnt; 24*4882a593Smuzhiyun u32 psc; 25*4882a593Smuzhiyun u32 arr; 26*4882a593Smuzhiyun u32 reserved; 27*4882a593Smuzhiyun u32 ccr1; 28*4882a593Smuzhiyun u32 ccr2; 29*4882a593Smuzhiyun u32 ccr3; 30*4882a593Smuzhiyun u32 ccr4; 31*4882a593Smuzhiyun u32 reserved1; 32*4882a593Smuzhiyun u32 dcr; 33*4882a593Smuzhiyun u32 dmar; 34*4882a593Smuzhiyun u32 tim2_5_or; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct gpt_regs *const gpt1_regs_ptr = 38*4882a593Smuzhiyun (struct gpt_regs *)TIM2_BASE; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Timer control1 register */ 41*4882a593Smuzhiyun #define GPT_CR1_CEN BIT(0) 42*4882a593Smuzhiyun #define GPT_MODE_AUTO_RELOAD BIT(7) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Auto reload register for free running config */ 45*4882a593Smuzhiyun #define GPT_FREE_RUNNING 0xFFFFFFFF 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Timer, HZ specific defines */ 48*4882a593Smuzhiyun #define CONFIG_STM32_HZ 1000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Timer Event Generation registers */ 51*4882a593Smuzhiyun #define TIM_EGR_UG BIT(0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54