1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_PERIPH_H 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_PERIPH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Peripherals required for pinmux configuration. List will 13*4882a593Smuzhiyun * grow with support for more devices getting added. 14*4882a593Smuzhiyun * Numbering based on interrupt table. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum periph_id { 18*4882a593Smuzhiyun UART1_GPIOA_9_10 = 0, 19*4882a593Smuzhiyun UART2_GPIOD_5_6, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun enum periph_clock { 23*4882a593Smuzhiyun USART1_CLOCK_CFG = 0, 24*4882a593Smuzhiyun USART2_CLOCK_CFG, 25*4882a593Smuzhiyun GPIO_A_CLOCK_CFG, 26*4882a593Smuzhiyun GPIO_B_CLOCK_CFG, 27*4882a593Smuzhiyun GPIO_C_CLOCK_CFG, 28*4882a593Smuzhiyun GPIO_D_CLOCK_CFG, 29*4882a593Smuzhiyun GPIO_E_CLOCK_CFG, 30*4882a593Smuzhiyun GPIO_F_CLOCK_CFG, 31*4882a593Smuzhiyun GPIO_G_CLOCK_CFG, 32*4882a593Smuzhiyun GPIO_H_CLOCK_CFG, 33*4882a593Smuzhiyun GPIO_I_CLOCK_CFG, 34*4882a593Smuzhiyun GPIO_J_CLOCK_CFG, 35*4882a593Smuzhiyun GPIO_K_CLOCK_CFG, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_PERIPH_H */ 39