1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2015 6*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _MACH_FMC_H_ 12*4882a593Smuzhiyun #define _MACH_FMC_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct stm32_fmc_regs { 15*4882a593Smuzhiyun u32 sdcr1; /* Control register 1 */ 16*4882a593Smuzhiyun u32 sdcr2; /* Control register 2 */ 17*4882a593Smuzhiyun u32 sdtr1; /* Timing register 1 */ 18*4882a593Smuzhiyun u32 sdtr2; /* Timing register 2 */ 19*4882a593Smuzhiyun u32 sdcmr; /* Mode register */ 20*4882a593Smuzhiyun u32 sdrtr; /* Refresh timing register */ 21*4882a593Smuzhiyun u32 sdsr; /* Status register */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * FMC registers base 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define STM32_SDRAM_FMC_BASE 0xA0000140 28*4882a593Smuzhiyun #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Control register SDCR */ 31*4882a593Smuzhiyun #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 32*4882a593Smuzhiyun #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 33*4882a593Smuzhiyun #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 34*4882a593Smuzhiyun #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 35*4882a593Smuzhiyun #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 36*4882a593Smuzhiyun #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 37*4882a593Smuzhiyun #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 38*4882a593Smuzhiyun #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 39*4882a593Smuzhiyun #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Timings register SDTR */ 42*4882a593Smuzhiyun #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 43*4882a593Smuzhiyun #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 44*4882a593Smuzhiyun #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 45*4882a593Smuzhiyun #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 46*4882a593Smuzhiyun #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 47*4882a593Smuzhiyun #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 48*4882a593Smuzhiyun #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define FMC_SDCMR_NRFS_SHIFT 5 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define FMC_SDCMR_MODE_NORMAL 0 54*4882a593Smuzhiyun #define FMC_SDCMR_MODE_START_CLOCK 1 55*4882a593Smuzhiyun #define FMC_SDCMR_MODE_PRECHARGE 2 56*4882a593Smuzhiyun #define FMC_SDCMR_MODE_AUTOREFRESH 3 57*4882a593Smuzhiyun #define FMC_SDCMR_MODE_WRITE_MODE 4 58*4882a593Smuzhiyun #define FMC_SDCMR_MODE_SELFREFRESH 5 59*4882a593Smuzhiyun #define FMC_SDCMR_MODE_POWERDOWN 6 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define FMC_SDCMR_BANK_1 (1 << 4) 62*4882a593Smuzhiyun #define FMC_SDCMR_BANK_2 (1 << 3) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define FMC_SDSR_BUSY (1 << 5) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define FMC_BUSY_WAIT() do { \ 69*4882a593Smuzhiyun __asm__ __volatile__ ("dsb" : : : "memory"); \ 70*4882a593Smuzhiyun while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ 71*4882a593Smuzhiyun ; \ 72*4882a593Smuzhiyun } while (0) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif /* _MACH_FMC_H_ */ 76