1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __STI_SDHCI_H__ 8*4882a593Smuzhiyun #define __STI_SDHCI_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define FLASHSS_MMC_CORE_CONFIG_1 0x400 11*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) 12*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define STI_FLASHSS_MMC_CORE_CONFIG_1 \ 15*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ 16*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define FLASHSS_MMC_CORE_CONFIG_2 0x404 19*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) 20*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) 21*4882a593Smuzhiyun #define MAX_BLK_LENGTH_1024 BIT(16) 22*4882a593Smuzhiyun #define BASE_CLK_FREQ_200 0xc8 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define STI_FLASHSS_MMC_CORE_CONFIG2 \ 25*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ 26*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_8BIT_EMMC | \ 27*4882a593Smuzhiyun MAX_BLK_LENGTH_1024 | \ 28*4882a593Smuzhiyun BASE_CLK_FREQ_200 << 0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ 31*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ 32*4882a593Smuzhiyun MAX_BLK_LENGTH_1024 | \ 33*4882a593Smuzhiyun BASE_CLK_FREQ_200) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define FLASHSS_MMC_CORE_CONFIG_3 0x408 36*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) 37*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) 38*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) 39*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) 40*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_SDMA BIT(0) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define STI_FLASHSS_MMC_CORE_CONFIG3 \ 43*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ 44*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ 45*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_3P3_VOLT | \ 46*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ 47*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_SDMA) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ 50*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ 51*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_3P3_VOLT | \ 52*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ 53*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_SDMA) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define FLASHSS_MMC_CORE_CONFIG_4 0x40c 56*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) 57*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) 58*4882a593Smuzhiyun #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define STI_FLASHSS_MMC_CORE_CONFIG4 \ 61*4882a593Smuzhiyun (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ 62*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ 63*4882a593Smuzhiyun FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define ST_MMC_CCONFIG_REG_5 0x210 66*4882a593Smuzhiyun #define SYSCONF_MMC1_ENABLE_BIT 3 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _STI_SDHCI_H_ */ 69