1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SPR_GPT_H 9*4882a593Smuzhiyun #define _SPR_GPT_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct gpt_regs { 12*4882a593Smuzhiyun u8 reserved[0x80]; 13*4882a593Smuzhiyun u32 control; 14*4882a593Smuzhiyun u32 status; 15*4882a593Smuzhiyun u32 compare; 16*4882a593Smuzhiyun u32 count; 17*4882a593Smuzhiyun u32 capture_re; 18*4882a593Smuzhiyun u32 capture_fe; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * TIMER_CONTROL register settings 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define GPT_PRESCALER_MASK 0x000F 26*4882a593Smuzhiyun #define GPT_PRESCALER_1 0x0000 27*4882a593Smuzhiyun #define GPT_PRESCALER_2 0x0001 28*4882a593Smuzhiyun #define GPT_PRESCALER_4 0x0002 29*4882a593Smuzhiyun #define GPT_PRESCALER_8 0x0003 30*4882a593Smuzhiyun #define GPT_PRESCALER_16 0x0004 31*4882a593Smuzhiyun #define GPT_PRESCALER_32 0x0005 32*4882a593Smuzhiyun #define GPT_PRESCALER_64 0x0006 33*4882a593Smuzhiyun #define GPT_PRESCALER_128 0x0007 34*4882a593Smuzhiyun #define GPT_PRESCALER_256 0x0008 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define GPT_MODE_SINGLE_SHOT 0x0010 37*4882a593Smuzhiyun #define GPT_MODE_AUTO_RELOAD 0x0000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define GPT_ENABLE 0x0020 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define GPT_CAPT_MODE_MASK 0x00C0 42*4882a593Smuzhiyun #define GPT_CAPT_MODE_NONE 0x0000 43*4882a593Smuzhiyun #define GPT_CAPT_MODE_RE 0x0040 44*4882a593Smuzhiyun #define GPT_CAPT_MODE_FE 0x0080 45*4882a593Smuzhiyun #define GPT_CAPT_MODE_BOTH 0x00C0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define GPT_INT_MATCH 0x0100 48*4882a593Smuzhiyun #define GPT_INT_FE 0x0200 49*4882a593Smuzhiyun #define GPT_INT_RE 0x0400 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * TIMER_STATUS register settings 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define GPT_STS_MATCH 0x0001 56*4882a593Smuzhiyun #define GPT_STS_FE 0x0002 57*4882a593Smuzhiyun #define GPT_STS_RE 0x0004 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * TIMER_COMPARE register settings 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define GPT_FREE_RUNNING 0xFFFF 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Timer, HZ specific defines */ 66*4882a593Smuzhiyun #define CONFIG_SPEAR_HZ 1000 67*4882a593Smuzhiyun #define CONFIG_SPEAR_HZ_CLOCK 8300000 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70