1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SPEAR_EMI_H__ 9*4882a593Smuzhiyun #define __SPEAR_EMI_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifdef CONFIG_SPEAR_EMI 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct emi_bank_regs { 14*4882a593Smuzhiyun u32 tap; 15*4882a593Smuzhiyun u32 tsdp; 16*4882a593Smuzhiyun u32 tdpw; 17*4882a593Smuzhiyun u32 tdpr; 18*4882a593Smuzhiyun u32 tdcs; 19*4882a593Smuzhiyun u32 control; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct emi_regs { 23*4882a593Smuzhiyun struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; 24*4882a593Smuzhiyun u32 tout; 25*4882a593Smuzhiyun u32 ack; 26*4882a593Smuzhiyun u32 irq; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define EMI_ACKMSK 0x40 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* control register definitions */ 32*4882a593Smuzhiyun #define EMI_CNTL_ENBBYTEW (1 << 2) 33*4882a593Smuzhiyun #define EMI_CNTL_ENBBYTER (1 << 3) 34*4882a593Smuzhiyun #define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39