1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_HARDWARE_H 9*4882a593Smuzhiyun #define _ASM_ARCH_HARDWARE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_SYS_USBD_BASE 0xE1100000 12*4882a593Smuzhiyun #define CONFIG_SYS_PLUG_BASE 0xE1200000 13*4882a593Smuzhiyun #define CONFIG_SYS_FIFO_BASE 0xE1000800 14*4882a593Smuzhiyun #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000 15*4882a593Smuzhiyun #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000 16*4882a593Smuzhiyun #define CONFIG_SYS_SMI_BASE 0xFC000000 17*4882a593Smuzhiyun #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 18*4882a593Smuzhiyun #define CONFIG_SPEAR_TIMERBASE 0xFC800000 19*4882a593Smuzhiyun #define CONFIG_SPEAR_MISCBASE 0xFCA80000 20*4882a593Smuzhiyun #define CONFIG_SPEAR_ETHBASE 0xE0800000 21*4882a593Smuzhiyun #define CONFIG_SPEAR_MPMCBASE 0xFC600000 22*4882a593Smuzhiyun #define CONFIG_SSP1_BASE 0xD0100000 23*4882a593Smuzhiyun #define CONFIG_SSP2_BASE 0xD0180000 24*4882a593Smuzhiyun #define CONFIG_SSP3_BASE 0xD8180000 25*4882a593Smuzhiyun #define CONFIG_GPIO_BASE 0xD8100000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_NAND_CLE (1 << 16) 28*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ALE (1 << 17) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #if defined(CONFIG_SPEAR600) 31*4882a593Smuzhiyun #define CONFIG_SYS_FSMC_BASE 0xD1800000 32*4882a593Smuzhiyun #define CONFIG_FSMC_NAND_BASE 0xD2000000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 35*4882a593Smuzhiyun #define CONFIG_SPEAR_BOOTSTRAPSHFT 16 36*4882a593Smuzhiyun #define CONFIG_SPEAR_BOOTSTRAPMASK 0xB 37*4882a593Smuzhiyun #define CONFIG_SPEAR_ONLYSNORBOOT 0xA 38*4882a593Smuzhiyun #define CONFIG_SPEAR_NORNANDBOOT 0xB 39*4882a593Smuzhiyun #define CONFIG_SPEAR_NORNAND8BOOT 0x8 40*4882a593Smuzhiyun #define CONFIG_SPEAR_NORNAND16BOOT 0x9 41*4882a593Smuzhiyun #define CONFIG_SPEAR_USBBOOT 0x8 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_SPEAR_MPMCREGS 100 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR300) 46*4882a593Smuzhiyun #define CONFIG_SYS_FSMC_BASE 0x94000000 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR310) 49*4882a593Smuzhiyun #define CONFIG_SYS_FSMC_BASE 0x44000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #undef CONFIG_SYS_NAND_CLE 52*4882a593Smuzhiyun #undef CONFIG_SYS_NAND_ALE 53*4882a593Smuzhiyun #define CONFIG_SYS_NAND_CLE (1 << 17) 54*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ALE (1 << 16) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CONFIG_SPEAR_EMIBASE 0x4F000000 57*4882a593Smuzhiyun #define CONFIG_SPEAR_RASBASE 0xB4000000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_SYS_MACB0_BASE 0xB0000000 60*4882a593Smuzhiyun #define CONFIG_SYS_MACB1_BASE 0xB0800000 61*4882a593Smuzhiyun #define CONFIG_SYS_MACB2_BASE 0xB1000000 62*4882a593Smuzhiyun #define CONFIG_SYS_MACB3_BASE 0xB1800000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR320) 65*4882a593Smuzhiyun #define CONFIG_SYS_FSMC_BASE 0x4C000000 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_SPEAR_EMIBASE 0x40000000 68*4882a593Smuzhiyun #define CONFIG_SPEAR_RASBASE 0xB3000000 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define CONFIG_SYS_MACB0_BASE 0xAA000000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun #endif /* _ASM_ARCH_HARDWARE_H */ 74