1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_RK3568_H 7*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_RK3568_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/arch-rockchip/sdram.h> 10*4882a593Smuzhiyun #include <asm/arch-rockchip/sdram_common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* store result of read and write training, for ddr_dq_eye tool in u-boot */ 13*4882a593Smuzhiyun #define RW_TRN_RESULT_ADDR (0x2000000 + 0x8000) /* 32M + 32k */ 14*4882a593Smuzhiyun #define PRINT_STEP 2 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #undef FSP_NUM 17*4882a593Smuzhiyun #undef CS_NUM 18*4882a593Smuzhiyun #undef BYTE_NUM 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define FSP_NUM 4 21*4882a593Smuzhiyun #define CS_NUM 4 22*4882a593Smuzhiyun #define BYTE_NUM 5 23*4882a593Smuzhiyun #define RD_DESKEW_NUM 128 24*4882a593Smuzhiyun #define WR_DESKEW_NUM 256 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define LP4_WIDTH_REF_MHZ_H 1560 27*4882a593Smuzhiyun #define LP4_RD_WIDTH_REF_H 25 28*4882a593Smuzhiyun #define LP4_WR_WIDTH_REF_H 24 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define LP4_WIDTH_REF_MHZ_L 1184 31*4882a593Smuzhiyun #define LP4_RD_WIDTH_REF_L 30 32*4882a593Smuzhiyun #define LP4_WR_WIDTH_REF_L 29 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DDR4_WIDTH_REF_MHZ_H 1560 35*4882a593Smuzhiyun #define DDR4_RD_WIDTH_REF_H 30 36*4882a593Smuzhiyun #define DDR4_WR_WIDTH_REF_H 22 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define DDR4_WIDTH_REF_MHZ_L 1184 39*4882a593Smuzhiyun #define DDR4_RD_WIDTH_REF_L 32 40*4882a593Smuzhiyun #define DDR4_WR_WIDTH_REF_L 26 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define LP3_WIDTH_REF_MHZ_H 1184 43*4882a593Smuzhiyun #define LP3_RD_WIDTH_REF_H 34 44*4882a593Smuzhiyun #define LP3_WR_WIDTH_REF_H 25 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define LP3_WIDTH_REF_MHZ_L 920 47*4882a593Smuzhiyun #define LP3_RD_WIDTH_REF_L 39 48*4882a593Smuzhiyun #define LP3_WR_WIDTH_REF_L 28 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define DDR3_WIDTH_REF_MHZ_H 1184 51*4882a593Smuzhiyun #define DDR3_RD_WIDTH_REF_H 32 52*4882a593Smuzhiyun #define DDR3_WR_WIDTH_REF_H 31 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define DDR3_WIDTH_REF_MHZ_L 920 55*4882a593Smuzhiyun #define DDR3_RD_WIDTH_REF_L 39 56*4882a593Smuzhiyun #define DDR3_WR_WIDTH_REF_L 34 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _ASM_ARCH_SDRAM_RK3568_H */ 59