1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_RK3399_H 8*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_RK3399_H 9*4882a593Smuzhiyun #include <asm/arch/sdram_common.h> 10*4882a593Smuzhiyun #include <asm/arch/sdram_msch.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rk3399_ddr_pctl_regs { 13*4882a593Smuzhiyun u32 denali_ctl[332]; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct rk3399_ddr_publ_regs { 17*4882a593Smuzhiyun u32 denali_phy[959]; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct rk3399_ddr_pi_regs { 21*4882a593Smuzhiyun u32 denali_pi[200]; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct rk3399_ddr_cic_regs { 25*4882a593Smuzhiyun u32 cic_ctrl0; 26*4882a593Smuzhiyun u32 cic_ctrl1; 27*4882a593Smuzhiyun u32 cic_idle_th; 28*4882a593Smuzhiyun u32 cic_cg_wait_th; 29*4882a593Smuzhiyun u32 cic_status0; 30*4882a593Smuzhiyun u32 cic_status1; 31*4882a593Smuzhiyun u32 cic_ctrl2; 32*4882a593Smuzhiyun u32 cic_ctrl3; 33*4882a593Smuzhiyun u32 cic_ctrl4; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* DENALI_CTL_00 */ 37*4882a593Smuzhiyun #define START 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* DENALI_CTL_68 */ 40*4882a593Smuzhiyun #define PWRUP_SREFRESH_EXIT (1 << 16) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* DENALI_CTL_274 */ 43*4882a593Smuzhiyun #define MEM_RST_VALID 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct msch_regs { 46*4882a593Smuzhiyun u32 coreid; 47*4882a593Smuzhiyun u32 revisionid; 48*4882a593Smuzhiyun u32 ddrconf; 49*4882a593Smuzhiyun u32 ddrsize; 50*4882a593Smuzhiyun union noc_ddrtiminga0 ddrtiminga0; 51*4882a593Smuzhiyun union noc_ddrtimingb0 ddrtimingb0; 52*4882a593Smuzhiyun union noc_ddrtimingc0 ddrtimingc0; 53*4882a593Smuzhiyun union noc_devtodev0 devtodev0; 54*4882a593Smuzhiyun u32 reserved0[(0x110 - 0x20) / 4]; 55*4882a593Smuzhiyun union noc_ddrmode ddrmode; 56*4882a593Smuzhiyun u32 reserved1[(0x1000 - 0x114) / 4]; 57*4882a593Smuzhiyun u32 agingx0; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct sdram_msch_timings { 61*4882a593Smuzhiyun union noc_ddrtiminga0 ddrtiminga0; 62*4882a593Smuzhiyun union noc_ddrtimingb0 ddrtimingb0; 63*4882a593Smuzhiyun union noc_ddrtimingc0 ddrtimingc0; 64*4882a593Smuzhiyun union noc_devtodev0 devtodev0; 65*4882a593Smuzhiyun union noc_ddrmode ddrmode; 66*4882a593Smuzhiyun u32 agingx0; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct rk3399_sdram_channel { 70*4882a593Smuzhiyun struct sdram_cap_info cap_info; 71*4882a593Smuzhiyun struct sdram_msch_timings noc_timings; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct rk3399_sdram_params { 75*4882a593Smuzhiyun struct rk3399_sdram_channel ch[2]; 76*4882a593Smuzhiyun struct sdram_base_params base; 77*4882a593Smuzhiyun struct rk3399_ddr_pctl_regs pctl_regs; 78*4882a593Smuzhiyun struct rk3399_ddr_pi_regs pi_regs; 79*4882a593Smuzhiyun struct rk3399_ddr_publ_regs phy_regs; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define PI_CA_TRAINING (1 << 0) 83*4882a593Smuzhiyun #define PI_WRITE_LEVELING (1 << 1) 84*4882a593Smuzhiyun #define PI_READ_GATE_TRAINING (1 << 2) 85*4882a593Smuzhiyun #define PI_READ_LEVELING (1 << 3) 86*4882a593Smuzhiyun #define PI_WDQ_LEVELING (1 << 4) 87*4882a593Smuzhiyun #define PI_FULL_TRAINING 0xff 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun enum { 90*4882a593Smuzhiyun STRIDE_128B = 0, 91*4882a593Smuzhiyun STRIDE_256B = 1, 92*4882a593Smuzhiyun STRIDE_512B = 2, 93*4882a593Smuzhiyun STRIDE_4KB = 3, 94*4882a593Smuzhiyun UN_STRIDE = 4, 95*4882a593Smuzhiyun PART_STRIDE = 5 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99