1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PX30_H 7 #define _ASM_ARCH_SDRAM_PX30_H 8 #include <asm/arch/sdram_common.h> 9 #include <asm/arch/sdram_msch.h> 10 #include <asm/arch/sdram_pctl_px30.h> 11 #include <asm/arch/sdram_phy_px30.h> 12 #include <asm/arch/sdram_phy_ron_rtt_px30.h> 13 14 #define SR_IDLE 93 15 #define PD_IDLE 13 16 17 /* PMUGRF */ 18 #define PMUGRF_OS_REG0 (0x200) 19 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) 20 21 /* DDR GRF */ 22 #define DDR_GRF_CON(n) (0 + (n) * 4) 23 #define DDR_GRF_STATUS_BASE (0X100) 24 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) 25 #define DDR_GRF_LP_CON (0x20) 26 27 #define SPLIT_MODE_32_L16_VALID (0) 28 #define SPLIT_MODE_32_H16_VALID (1) 29 #define SPLIT_MODE_16_L8_VALID (2) 30 #define SPLIT_MODE_16_H8_VALID (3) 31 32 #define DDR_GRF_SPLIT_CON (0x8) 33 #define SPLIT_MODE_MASK (0x3) 34 #define SPLIT_MODE_OFFSET (9) 35 #define SPLIT_BYPASS_MASK (1) 36 #define SPLIT_BYPASS_OFFSET (8) 37 #define SPLIT_SIZE_MASK (0xff) 38 #define SPLIT_SIZE_OFFSET (0) 39 40 /* CRU define */ 41 /* CRU_PLL_CON0 */ 42 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) 43 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) 44 #define FBDIV(n) ((0xFFF << 16) | (n)) 45 46 /* CRU_PLL_CON1 */ 47 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) 48 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) 49 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) 50 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) 51 #define LOCK(n) (((n) >> 10) & 0x1) 52 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) 53 #define REFDIV(n) ((0x3F << 16) | (n)) 54 55 /* CRU_MODE */ 56 #define CLOCK_FROM_XIN_OSC (0) 57 #define CLOCK_FROM_PLL (1) 58 #define CLOCK_FROM_RTC_32K (2) 59 #define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4)) 60 61 /* CRU_SOFTRESET_CON1 */ 62 #define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6)) 63 #define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5)) 64 #define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4)) 65 66 /* CRU_SOFTRESET_CON2 */ 67 #define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2)) 68 #define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0)) 69 70 /* CRU register */ 71 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 72 #define CRU_MODE (0xa0) 73 #define CRU_GLB_CNT_TH (0xb0) 74 #define CRU_CLKSEL_CON_BASE 0x100 75 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) 76 #define CRU_CLKGATE_CON_BASE 0x200 77 #define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) 78 #define CRU_CLKSFTRST_CON_BASE 0x300 79 #define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) 80 81 u8 ddr_cfg_2_rbc[] = { 82 /* 83 * [6:4] max row: 13+n 84 * [3] bank(0:4bank,1:8bank) 85 * [2:0] col(10+n) 86 */ 87 ((5 << 4) | (1 << 3) | 0), /* 0 */ 88 ((5 << 4) | (1 << 3) | 1), /* 1 */ 89 ((4 << 4) | (1 << 3) | 2), /* 2 */ 90 ((3 << 4) | (1 << 3) | 3), /* 3 */ 91 ((2 << 4) | (1 << 3) | 4), /* 4 */ 92 ((5 << 4) | (0 << 3) | 2), /* 5 */ 93 ((4 << 4) | (1 << 3) | 2), /* 6 */ 94 /*((0<<3)|3),*/ /* 12 for ddr4 */ 95 /*((1<<3)|1),*/ /* 13 B,C exchange for rkvdec */ 96 }; 97 98 /* 99 * for ddr4 if ddrconfig=7, upctl should set 7 and noc should 100 * set to 1 for more efficient. 101 * noc ddrconf, upctl addrmap 102 * 1 7 103 * 2 8 104 * 3 9 105 * 12 10 106 * 5 11 107 */ 108 u8 d4_rbc_2_d3_rbc[] = { 109 1, /* 7 */ 110 2, /* 8 */ 111 3, /* 9 */ 112 12, /* 10 */ 113 5, /* 11 */ 114 }; 115 116 /* 117 * row higher than cs should be disabled by set to 0xf 118 * rank addrmap calculate by real cap. 119 */ 120 u32 addrmap[][8] = { 121 /* map0 map1, map2, map3, map4, map5 122 * map6, map7, map8 123 * ------------------------------------------------------- 124 * bk2-0 col 5-2 col 9-6 col 11-10 row 11-0 125 * row 15-12 row 17-16 bg1,0 126 * ------------------------------------------------------- 127 * 4,3,2 5-2 9-6 6 128 * 3,2 129 */ 130 {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, 131 0x05050505, 0x00000505, 0x3f3f}, /* 0 */ 132 {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 133 0x06060606, 0x06060606, 0x3f3f}, /* 1 */ 134 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 135 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */ 136 {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 137 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */ 138 {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 139 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ 140 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 141 0x06060606, 0x00000606, 0x3f3f}, /* 5 */ 142 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 143 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */ 144 {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, 145 0x06060606, 0x00000606, 0x0600}, /* 7 */ 146 {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 147 0x07070707, 0x00000f07, 0x0700}, /* 8 */ 148 {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 149 0x08080808, 0x00000f0f, 0x0801}, /* 9 */ 150 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 151 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 152 {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 153 0x06060606, 0x00000606, 0x3f00}, /* 11 */ 154 /* when ddr4 12 map to 10, when ddr3 12 unused */ 155 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 156 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 157 {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606, 158 0x06060606, 0x00000606, 0x3f3f}, /* 13 */ 159 }; 160 161 struct px30_ddr_grf_regs { 162 u32 ddr_grf_con[4]; 163 u32 reserved1[(0x20 - 0x10) / 4]; 164 u32 ddr_grf_lp_con; 165 u32 reserved2[(0x100 - 0x24) / 4]; 166 u32 ddr_grf_status[11]; 167 }; 168 169 struct msch_regs { 170 u32 coreid; 171 u32 revisionid; 172 u32 deviceconf; 173 u32 devicesize; 174 u32 ddrtiminga0; 175 u32 ddrtimingb0; 176 u32 ddrtimingc0; 177 u32 devtodev0; 178 u32 reserved1[(0x110 - 0x20) / 4]; 179 u32 ddrmode; 180 u32 ddr4timing; 181 u32 reserved2[(0x1000 - 0x118) / 4]; 182 u32 agingx0; 183 u32 reserved3[(0x1040 - 0x1004) / 4]; 184 u32 aging0; 185 u32 aging1; 186 u32 aging2; 187 u32 aging3; 188 }; 189 190 struct sdram_msch_timings { 191 union noc_ddrtiminga0 ddrtiminga0; 192 union noc_ddrtimingb0 ddrtimingb0; 193 union noc_ddrtimingc0 ddrtimingc0; 194 union noc_devtodev0 devtodev0; 195 union noc_ddrmode ddrmode; 196 union noc_ddr4timing ddr4timing; 197 u32 agingx0; 198 }; 199 200 struct px30_sdram_channel { 201 struct sdram_cap_info cap_info; 202 struct sdram_msch_timings noc_timings; 203 }; 204 205 struct px30_sdram_params { 206 struct px30_sdram_channel ch; 207 struct sdram_base_params base; 208 struct ddr_pctl_regs pctl_regs; 209 struct ddr_phy_regs phy_regs; 210 struct ddr_phy_skew *skew; 211 }; 212 #endif 213