1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_MSCH_H 7*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_MSCH_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun union noc_ddrtiminga0 { 10*4882a593Smuzhiyun u32 d32; 11*4882a593Smuzhiyun struct { 12*4882a593Smuzhiyun unsigned acttoact : 6; 13*4882a593Smuzhiyun unsigned reserved0 : 2; 14*4882a593Smuzhiyun unsigned rdtomiss : 6; 15*4882a593Smuzhiyun unsigned reserved1 : 2; 16*4882a593Smuzhiyun unsigned wrtomiss : 6; 17*4882a593Smuzhiyun unsigned reserved2 : 2; 18*4882a593Smuzhiyun unsigned readlatency : 8; 19*4882a593Smuzhiyun } b; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun union noc_ddrtimingb0 { 23*4882a593Smuzhiyun u32 d32; 24*4882a593Smuzhiyun struct { 25*4882a593Smuzhiyun unsigned rdtowr : 5; 26*4882a593Smuzhiyun unsigned reserved0 : 3; 27*4882a593Smuzhiyun unsigned wrtord : 5; 28*4882a593Smuzhiyun unsigned reserved1 : 3; 29*4882a593Smuzhiyun unsigned rrd : 4; 30*4882a593Smuzhiyun unsigned reserved2 : 4; 31*4882a593Smuzhiyun unsigned faw : 6; 32*4882a593Smuzhiyun unsigned reserved3 : 2; 33*4882a593Smuzhiyun } b; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun union noc_ddrtimingc0 { 37*4882a593Smuzhiyun u32 d32; 38*4882a593Smuzhiyun struct { 39*4882a593Smuzhiyun unsigned burstpenalty : 4; 40*4882a593Smuzhiyun unsigned reserved0 : 4; 41*4882a593Smuzhiyun unsigned wrtomwr : 6; 42*4882a593Smuzhiyun unsigned reserved1 : 18; 43*4882a593Smuzhiyun } b; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun union noc_ddrtimingl { 47*4882a593Smuzhiyun u32 d32; 48*4882a593Smuzhiyun struct { 49*4882a593Smuzhiyun unsigned ccdl : 3; 50*4882a593Smuzhiyun unsigned wrtordl : 5; 51*4882a593Smuzhiyun unsigned rrdl : 4; 52*4882a593Smuzhiyun unsigned reserved : 20; 53*4882a593Smuzhiyun } b; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun union noc_devtodev0 { 57*4882a593Smuzhiyun u32 d32; 58*4882a593Smuzhiyun struct { 59*4882a593Smuzhiyun unsigned busrdtord : 3; 60*4882a593Smuzhiyun unsigned reserved0 : 1; 61*4882a593Smuzhiyun unsigned busrdtowr : 3; 62*4882a593Smuzhiyun unsigned reserved1 : 1; 63*4882a593Smuzhiyun unsigned buswrtord : 3; 64*4882a593Smuzhiyun unsigned reserved2 : 1; 65*4882a593Smuzhiyun unsigned buswrtowr : 3; 66*4882a593Smuzhiyun unsigned reserved3 : 17; 67*4882a593Smuzhiyun } b; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun union noc_devtodev_rv1126 { 71*4882a593Smuzhiyun u32 d32; 72*4882a593Smuzhiyun struct { 73*4882a593Smuzhiyun unsigned busrdtord : 3; 74*4882a593Smuzhiyun unsigned reserved0 : 1; 75*4882a593Smuzhiyun unsigned busrdtowr : 4; 76*4882a593Smuzhiyun unsigned buswrtord : 4; 77*4882a593Smuzhiyun unsigned buswrtowr : 3; 78*4882a593Smuzhiyun unsigned reserved2 : 17; 79*4882a593Smuzhiyun } b; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun union noc_ddrmode { 83*4882a593Smuzhiyun u32 d32; 84*4882a593Smuzhiyun struct { 85*4882a593Smuzhiyun unsigned autoprecharge : 1; 86*4882a593Smuzhiyun unsigned bypassfiltering : 1; 87*4882a593Smuzhiyun unsigned fawbank : 1; 88*4882a593Smuzhiyun unsigned burstsize : 2; 89*4882a593Smuzhiyun unsigned mwrsize : 2; 90*4882a593Smuzhiyun unsigned reserved2 : 1; 91*4882a593Smuzhiyun unsigned forceorder : 8; 92*4882a593Smuzhiyun unsigned forceorderstate : 8; 93*4882a593Smuzhiyun unsigned reserved3 : 8; 94*4882a593Smuzhiyun } b; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun union noc_ddr4timing { 98*4882a593Smuzhiyun u32 d32; 99*4882a593Smuzhiyun struct { 100*4882a593Smuzhiyun unsigned ccdl : 3; 101*4882a593Smuzhiyun unsigned wrtordl : 5; 102*4882a593Smuzhiyun unsigned rrdl : 4; 103*4882a593Smuzhiyun unsigned reserved1 : 20; 104*4882a593Smuzhiyun } b; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif 108