1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ROCKCHIP_DMC_H_ 7*4882a593Smuzhiyun #define __ROCKCHIP_DMC_H_ 8*4882a593Smuzhiyun #include <dm.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef MHZ 11*4882a593Smuzhiyun #define MHZ (1000 * 1000) 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun int rockchip_ddrclk_sip_set_rate_v2(unsigned long drate); 15*4882a593Smuzhiyun unsigned long rockchip_ddrclk_sip_recalc_rate_v2(void); 16*4882a593Smuzhiyun unsigned long rockchip_ddrclk_sip_round_rate_v2(unsigned long rate); 17*4882a593Smuzhiyun int rockchip_dmcfreq_probe(struct udevice *dev); 18*4882a593Smuzhiyun int set_ddr_freq(unsigned long freq); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif 21