1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Google, Inc 3*4882a593Smuzhiyun * (C) Copyright 2008-2014 Rockchip Electronics 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_PWM_H 9*4882a593Smuzhiyun #define _ASM_ARCH_PWM_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rockchip_pwm_regs { 12*4882a593Smuzhiyun unsigned long duty; 13*4882a593Smuzhiyun unsigned long period; 14*4882a593Smuzhiyun unsigned long cntr; 15*4882a593Smuzhiyun unsigned long ctrl; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define PWM_CTRL_TIMER_EN (1 << 0) 19*4882a593Smuzhiyun #define PWM_CTRL_OUTPUT_EN (1 << 3) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define RK_PWM_DISABLE (0 << 0) 22*4882a593Smuzhiyun #define RK_PWM_ENABLE (1 << 0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PWM_ONE_SHOT (0 << 1) 25*4882a593Smuzhiyun #define PWM_CONTINUOUS (1 << 1) 26*4882a593Smuzhiyun #define RK_PWM_CAPTURE (1 << 2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PWM_DUTY_POSTIVE (1 << 3) 29*4882a593Smuzhiyun #define PWM_DUTY_NEGATIVE (0 << 3) 30*4882a593Smuzhiyun #define PWM_DUTY_MASK (1 << 3) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PWM_INACTIVE_POSTIVE (1 << 4) 33*4882a593Smuzhiyun #define PWM_INACTIVE_NEGATIVE (0 << 4) 34*4882a593Smuzhiyun #define PWM_INACTIVE_MASK (1 << 4) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PWM_OUTPUT_LEFT (0 << 5) 37*4882a593Smuzhiyun #define PWM_OUTPUT_CENTER (1 << 5) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PWM_LOCK (1 << 6) 40*4882a593Smuzhiyun #define PWM_UNLOCK (0 << 6) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define PWM_LP_ENABLE (1 << 8) 43*4882a593Smuzhiyun #define PWM_LP_DISABLE (0 << 8) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PWM_SEL_SCALE_CLK (1 << 9) 46*4882a593Smuzhiyun #define PWM_SEL_SRC_CLK (0 << 9) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49