1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * Author: Zhihuan He <huan.he@rock-chips.com> 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_PMU_RV1108_H 8*4882a593Smuzhiyun #define _ASM_ARCH_PMU_RV1108_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct rv1108_pmu { 11*4882a593Smuzhiyun u32 wakeup_cfg[3]; 12*4882a593Smuzhiyun u32 reserved0[2]; 13*4882a593Smuzhiyun u32 pwrmode_core_con; 14*4882a593Smuzhiyun u32 pwrmode_common_con; 15*4882a593Smuzhiyun u32 sft_con; 16*4882a593Smuzhiyun u32 reserved1[7]; 17*4882a593Smuzhiyun u32 bus_idle_req; 18*4882a593Smuzhiyun u32 bus_idle_st; 19*4882a593Smuzhiyun u32 reserved2; 20*4882a593Smuzhiyun u32 osc_cnt; 21*4882a593Smuzhiyun u32 plllock_cnt; 22*4882a593Smuzhiyun u32 reserved3; 23*4882a593Smuzhiyun u32 stable_cnt; 24*4882a593Smuzhiyun u32 reserved4; 25*4882a593Smuzhiyun u32 wakeup_rst_clr_cnt; 26*4882a593Smuzhiyun u32 ddr_sref_st; 27*4882a593Smuzhiyun u32 sys_reg[4]; 28*4882a593Smuzhiyun u32 timeout_cnt; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun check_member(rv1108_pmu, timeout_cnt, 0x0074); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun enum { /* PMU_SFT_CON */ 34*4882a593Smuzhiyun DDR_IO_RET_SHIFT = 11, 35*4882a593Smuzhiyun DDR_IO_RET_EN = 1 << DDR_IO_RET_SHIFT, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun 40