1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ 8*4882a593Smuzhiyun #define __SOC_ROCKCHIP_RK3399_PMU_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct rk3399_pmu_regs { 11*4882a593Smuzhiyun u32 pmu_wakeup_cfg[5]; 12*4882a593Smuzhiyun u32 pmu_pwrdn_con; 13*4882a593Smuzhiyun u32 pmu_pwrdn_st; 14*4882a593Smuzhiyun u32 pmu_pll_con; 15*4882a593Smuzhiyun u32 pmu_pwrmode_con; 16*4882a593Smuzhiyun u32 pmu_sft_con; 17*4882a593Smuzhiyun u32 pmu_int_con; 18*4882a593Smuzhiyun u32 pmu_int_st; 19*4882a593Smuzhiyun u32 pmu_gpio0_pos_int_con; 20*4882a593Smuzhiyun u32 pmu_gpio0_net_int_con; 21*4882a593Smuzhiyun u32 pmu_gpio1_pos_int_con; 22*4882a593Smuzhiyun u32 pmu_gpio1_net_int_con; 23*4882a593Smuzhiyun u32 pmu_gpio0_pos_int_st; 24*4882a593Smuzhiyun u32 pmu_gpio0_net_int_st; 25*4882a593Smuzhiyun u32 pmu_gpio1_pos_int_st; 26*4882a593Smuzhiyun u32 pmu_gpio1_net_int_st; 27*4882a593Smuzhiyun u32 pmu_pwrdn_inten; 28*4882a593Smuzhiyun u32 pmu_pwrdn_status; 29*4882a593Smuzhiyun u32 pmu_wakeup_status; 30*4882a593Smuzhiyun u32 pmu_bus_clr; 31*4882a593Smuzhiyun u32 pmu_bus_idle_req; 32*4882a593Smuzhiyun u32 pmu_bus_idle_st; 33*4882a593Smuzhiyun u32 pmu_bus_idle_ack; 34*4882a593Smuzhiyun u32 pmu_cci500_con; 35*4882a593Smuzhiyun u32 pmu_adb400_con; 36*4882a593Smuzhiyun u32 pmu_adb400_st; 37*4882a593Smuzhiyun u32 pmu_power_st; 38*4882a593Smuzhiyun u32 pmu_core_pwr_st; 39*4882a593Smuzhiyun u32 pmu_osc_cnt; 40*4882a593Smuzhiyun u32 pmu_plllock_cnt; 41*4882a593Smuzhiyun u32 pmu_pllrst_cnt; 42*4882a593Smuzhiyun u32 pmu_stable_cnt; 43*4882a593Smuzhiyun u32 pmu_ddrio_pwron_cnt; 44*4882a593Smuzhiyun u32 pmu_wakeup_rst_clr_cnt; 45*4882a593Smuzhiyun u32 pmu_ddr_sref_st; 46*4882a593Smuzhiyun u32 pmu_scu_l_pwrdn_cnt; 47*4882a593Smuzhiyun u32 pmu_scu_l_pwrup_cnt; 48*4882a593Smuzhiyun u32 pmu_scu_b_pwrdn_cnt; 49*4882a593Smuzhiyun u32 pmu_scu_b_pwrup_cnt; 50*4882a593Smuzhiyun u32 pmu_gpu_pwrdn_cnt; 51*4882a593Smuzhiyun u32 pmu_gpu_pwrup_cnt; 52*4882a593Smuzhiyun u32 pmu_center_pwrdn_cnt; 53*4882a593Smuzhiyun u32 pmu_center_pwrup_cnt; 54*4882a593Smuzhiyun u32 pmu_timeout_cnt; 55*4882a593Smuzhiyun u32 pmu_cpu0apm_con; 56*4882a593Smuzhiyun u32 pmu_cpu1apm_con; 57*4882a593Smuzhiyun u32 pmu_cpu2apm_con; 58*4882a593Smuzhiyun u32 pmu_cpu3apm_con; 59*4882a593Smuzhiyun u32 pmu_cpu0bpm_con; 60*4882a593Smuzhiyun u32 pmu_cpu1bpm_con; 61*4882a593Smuzhiyun u32 pmu_noc_auto_ena; 62*4882a593Smuzhiyun u32 pmu_pwrdn_con1; 63*4882a593Smuzhiyun u32 reserved0[0x4]; 64*4882a593Smuzhiyun u32 pmu_sys_reg_reg0; 65*4882a593Smuzhiyun u32 pmu_sys_reg_reg1; 66*4882a593Smuzhiyun u32 pmu_sys_reg_reg2; 67*4882a593Smuzhiyun u32 pmu_sys_reg_reg3; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ 73