1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2014 Rockchip Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_ARCH_PMU_RK3288_H 10*4882a593Smuzhiyun #define _ASM_ARCH_PMU_RK3288_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rk3288_pmu { 13*4882a593Smuzhiyun u32 wakeup_cfg[2]; 14*4882a593Smuzhiyun u32 pwrdn_con; 15*4882a593Smuzhiyun u32 pwrdn_st; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun u32 idle_req; 18*4882a593Smuzhiyun u32 idle_st; 19*4882a593Smuzhiyun u32 pwrmode_con; 20*4882a593Smuzhiyun u32 pwr_state; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun u32 osc_cnt; 23*4882a593Smuzhiyun u32 pll_cnt; 24*4882a593Smuzhiyun u32 stabl_cnt; 25*4882a593Smuzhiyun u32 ddr0io_pwron_cnt; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u32 ddr1io_pwron_cnt; 28*4882a593Smuzhiyun u32 core_pwrdn_cnt; 29*4882a593Smuzhiyun u32 core_pwrup_cnt; 30*4882a593Smuzhiyun u32 gpu_pwrdn_cnt; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u32 gpu_pwrup_cnt; 33*4882a593Smuzhiyun u32 wakeup_rst_clr_cnt; 34*4882a593Smuzhiyun u32 sft_con; 35*4882a593Smuzhiyun u32 ddr_sref_st; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u32 int_con; 38*4882a593Smuzhiyun u32 int_st; 39*4882a593Smuzhiyun u32 boot_addr_sel; 40*4882a593Smuzhiyun u32 grf_con; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u32 gpio_sr; 43*4882a593Smuzhiyun u32 gpio0pull[3]; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun u32 gpio0drv[3]; 46*4882a593Smuzhiyun u32 gpio_op; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun u32 gpio0_sel18; /* 0x80 */ 49*4882a593Smuzhiyun u32 gpio0_iomux[4]; /* a, b, c, d */ 50*4882a593Smuzhiyun u32 sys_reg[4]; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun check_member(rk3288_pmu, sys_reg[3], 0x00a0); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum { 55*4882a593Smuzhiyun PMU_GPIO0_A = 0, 56*4882a593Smuzhiyun PMU_GPIO0_B, 57*4882a593Smuzhiyun PMU_GPIO0_C, 58*4882a593Smuzhiyun PMU_GPIO0_D, 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* PMU_GPIO0_B_IOMUX */ 62*4882a593Smuzhiyun enum { 63*4882a593Smuzhiyun GPIO0_B7_SHIFT = 14, 64*4882a593Smuzhiyun GPIO0_B7_MASK = 1, 65*4882a593Smuzhiyun GPIO0_B7_GPIOB7 = 0, 66*4882a593Smuzhiyun GPIO0_B7_I2C0PMU_SDA, 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun GPIO0_B5_SHIFT = 10, 69*4882a593Smuzhiyun GPIO0_B5_MASK = 1, 70*4882a593Smuzhiyun GPIO0_B5_GPIOB5 = 0, 71*4882a593Smuzhiyun GPIO0_B5_CLK_27M, 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun GPIO0_B2_SHIFT = 4, 74*4882a593Smuzhiyun GPIO0_B2_MASK = 1, 75*4882a593Smuzhiyun GPIO0_B2_GPIOB2 = 0, 76*4882a593Smuzhiyun GPIO0_B2_TSADC_INT, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* PMU_GPIO0_C_IOMUX */ 80*4882a593Smuzhiyun enum { 81*4882a593Smuzhiyun GPIO0_C1_SHIFT = 2, 82*4882a593Smuzhiyun GPIO0_C1_MASK = 3, 83*4882a593Smuzhiyun GPIO0_C1_GPIOC1 = 0, 84*4882a593Smuzhiyun GPIO0_C1_TEST_CLKOUT, 85*4882a593Smuzhiyun GPIO0_C1_CLKT1_27M, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun GPIO0_C0_SHIFT = 0, 88*4882a593Smuzhiyun GPIO0_C0_MASK = 1, 89*4882a593Smuzhiyun GPIO0_C0_GPIOC0 = 0, 90*4882a593Smuzhiyun GPIO0_C0_I2C0PMU_SCL, 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif 94