1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 SAMSUNG Electronics 3*4882a593Smuzhiyun * Jaehoon Chung <jh80.chung@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_I2C_H 9*4882a593Smuzhiyun #define __ASM_ARCH_I2C_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct i2c_regs { 12*4882a593Smuzhiyun u32 con; 13*4882a593Smuzhiyun u32 clkdiv; 14*4882a593Smuzhiyun u32 mrxaddr; 15*4882a593Smuzhiyun u32 mrxraddr; 16*4882a593Smuzhiyun u32 mtxcnt; 17*4882a593Smuzhiyun u32 mrxcnt; 18*4882a593Smuzhiyun u32 ien; 19*4882a593Smuzhiyun u32 ipd; 20*4882a593Smuzhiyun u32 fcnt; 21*4882a593Smuzhiyun u32 reserved0[0x37]; 22*4882a593Smuzhiyun u32 txdata[8]; 23*4882a593Smuzhiyun u32 reserved1[0x38]; 24*4882a593Smuzhiyun u32 rxdata[8]; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Control register */ 28*4882a593Smuzhiyun #define I2C_CON_EN (1 << 0) 29*4882a593Smuzhiyun #define I2C_CON_MOD(mod) ((mod) << 1) 30*4882a593Smuzhiyun #define I2C_MODE_TX 0x00 31*4882a593Smuzhiyun #define I2C_MODE_TRX 0x01 32*4882a593Smuzhiyun #define I2C_MODE_RX 0x02 33*4882a593Smuzhiyun #define I2C_MODE_RRX 0x03 34*4882a593Smuzhiyun #define I2C_CON_MASK (3 << 1) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define I2C_CON_START (1 << 3) 37*4882a593Smuzhiyun #define I2C_CON_STOP (1 << 4) 38*4882a593Smuzhiyun #define I2C_CON_LASTACK (1 << 5) 39*4882a593Smuzhiyun #define I2C_CON_ACTACK (1 << 6) 40*4882a593Smuzhiyun #define I2C_CON_TUNING_MASK (0xff << 8) 41*4882a593Smuzhiyun #define I2C_CON_SDA_CFG(cfg) ((cfg) << 8) 42*4882a593Smuzhiyun #define I2C_CON_STA_CFG(cfg) ((cfg) << 12) 43*4882a593Smuzhiyun #define I2C_CON_STO_CFG(cfg) ((cfg) << 14) 44*4882a593Smuzhiyun #define I2C_CON_VERSION GENMASK_ULL(24, 16) 45*4882a593Smuzhiyun #define I2C_CON_VERSION_SHIFT 16 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Clock dividor register */ 48*4882a593Smuzhiyun #define I2C_CLK_DIV_HIGH_SHIFT 16 49*4882a593Smuzhiyun #define I2C_CLKDIV_VAL(divl, divh) \ 50*4882a593Smuzhiyun (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* the slave address accessed for master rx mode */ 53*4882a593Smuzhiyun #define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* the slave register address accessed for master rx mode */ 56*4882a593Smuzhiyun #define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* interrupt enable register */ 59*4882a593Smuzhiyun #define I2C_BTFIEN (1 << 0) 60*4882a593Smuzhiyun #define I2C_BRFIEN (1 << 1) 61*4882a593Smuzhiyun #define I2C_MBTFIEN (1 << 2) 62*4882a593Smuzhiyun #define I2C_MBRFIEN (1 << 3) 63*4882a593Smuzhiyun #define I2C_STARTIEN (1 << 4) 64*4882a593Smuzhiyun #define I2C_STOPIEN (1 << 5) 65*4882a593Smuzhiyun #define I2C_NAKRCVIEN (1 << 6) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* interrupt pending register */ 68*4882a593Smuzhiyun #define I2C_BTFIPD (1 << 0) 69*4882a593Smuzhiyun #define I2C_BRFIPD (1 << 1) 70*4882a593Smuzhiyun #define I2C_MBTFIPD (1 << 2) 71*4882a593Smuzhiyun #define I2C_MBRFIPD (1 << 3) 72*4882a593Smuzhiyun #define I2C_STARTIPD (1 << 4) 73*4882a593Smuzhiyun #define I2C_STOPIPD (1 << 5) 74*4882a593Smuzhiyun #define I2C_NAKRCVIPD (1 << 6) 75*4882a593Smuzhiyun #define I2C_IPD_ALL_CLEAN 0x7f 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78