1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_GRF_RK3562_H 7*4882a593Smuzhiyun #define _ASM_ARCH_GRF_RK3562_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3562_pmu_grf { 12*4882a593Smuzhiyun /* pmugrf */ 13*4882a593Smuzhiyun uint32_t reserved1[(0x0100 - 0x0000) / 4]; /* address offset: 0x0000 */ 14*4882a593Smuzhiyun uint32_t soc_con[13]; /* address offset: 0x0100 */ 15*4882a593Smuzhiyun uint32_t soc_status[1]; /* address offset: 0x0134 */ 16*4882a593Smuzhiyun uint32_t reserved2[(0x0180 - 0x0134) / 4 - 1]; /* address offset: 0x0138 */ 17*4882a593Smuzhiyun uint32_t pvtm_con[1]; /* address offset: 0x0180 */ 18*4882a593Smuzhiyun uint32_t reserved3[(0x0200 - 0x0180) / 4 - 1]; /* address offset: 0x0184 */ 19*4882a593Smuzhiyun uint32_t os_reg[12]; /* address offset: 0x0200 */ 20*4882a593Smuzhiyun uint32_t reset_function_status; /* address offset: 0x0230 */ 21*4882a593Smuzhiyun uint32_t reset_function_clr; /* address offset: 0x0234 */ 22*4882a593Smuzhiyun uint32_t reserved4[(0x0380 - 0x0234) / 4 - 1]; /* address offset: 0x0238 */ 23*4882a593Smuzhiyun uint32_t sig_detect_con; /* address offset: 0x0380 */ 24*4882a593Smuzhiyun uint32_t reserved5[(0x0390 - 0x0380) / 4 - 1]; /* address offset: 0x0384 */ 25*4882a593Smuzhiyun uint32_t sig_detect_status; /* address offset: 0x0390 */ 26*4882a593Smuzhiyun uint32_t reserved6[(0x03a0 - 0x0390) / 4 - 1]; /* address offset: 0x0394 */ 27*4882a593Smuzhiyun uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */ 28*4882a593Smuzhiyun uint32_t reserved7[(0x03b0 - 0x03a0) / 4 - 1]; /* address offset: 0x03a4 */ 29*4882a593Smuzhiyun uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun check_member(rk3562_pmu_grf, sdmmc_det_counter, 0x03b0); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct rk3562_grf { 35*4882a593Smuzhiyun /* sysgrf */ 36*4882a593Smuzhiyun uint32_t reserved1[(0x0400 - 0x0000) / 4]; /* address offset: 0x0000 */ 37*4882a593Smuzhiyun uint32_t soc_con[7]; /* address offset: 0x0400 */ 38*4882a593Smuzhiyun uint32_t reserved2[(0x0430 - 0x0400) / 4 - 7]; /* address offset: 0x041c */ 39*4882a593Smuzhiyun uint32_t soc_status[3]; /* address offset: 0x0430 */ 40*4882a593Smuzhiyun uint32_t reserved3; /* address offset: 0x043c */ 41*4882a593Smuzhiyun uint32_t biu_con[2]; /* address offset: 0x0440 */ 42*4882a593Smuzhiyun uint32_t reserved4[(0x0460 - 0x0440) / 4 - 2]; /* address offset: 0x0448 */ 43*4882a593Smuzhiyun uint32_t ram_con; /* address offset: 0x0460 */ 44*4882a593Smuzhiyun uint32_t core_ram_con; /* address offset: 0x0464 */ 45*4882a593Smuzhiyun uint32_t reserved5[(0x0500 - 0x0464) / 4 - 1]; /* address offset: 0x0468 */ 46*4882a593Smuzhiyun uint32_t cpu_con[2]; /* address offset: 0x0500 */ 47*4882a593Smuzhiyun uint32_t reserved6[(0x0510 - 0x0500) / 4 - 2]; /* address offset: 0x0508 */ 48*4882a593Smuzhiyun uint32_t cpu_status[2]; /* address offset: 0x0510 */ 49*4882a593Smuzhiyun uint32_t reserved7[(0x0520 - 0x0510) / 4 - 2]; /* address offset: 0x0518 */ 50*4882a593Smuzhiyun uint32_t vi_con[2]; /* address offset: 0x0520 */ 51*4882a593Smuzhiyun uint32_t reserved8[(0x0530 - 0x0520) / 4 - 2]; /* address offset: 0x0528 */ 52*4882a593Smuzhiyun uint32_t vi_status[1]; /* address offset: 0x0530 */ 53*4882a593Smuzhiyun uint32_t reserved9[(0x0570 - 0x0530) / 4 - 1]; /* address offset: 0x0534 */ 54*4882a593Smuzhiyun uint32_t gpu_con[2]; /* address offset: 0x0570 */ 55*4882a593Smuzhiyun uint32_t reserved10[(0x0580 - 0x0570) / 4 - 2]; /* address offset: 0x0578 */ 56*4882a593Smuzhiyun uint32_t tsadc_con; /* address offset: 0x0580 */ 57*4882a593Smuzhiyun uint32_t reserved11[(0x05d0 - 0x0580) / 4 - 1]; /* address offset: 0x0584 */ 58*4882a593Smuzhiyun uint32_t vo_con[2]; /* address offset: 0x05d0 */ 59*4882a593Smuzhiyun uint32_t reserved12[(0x0600 - 0x05d0) / 4 - 2]; /* address offset: 0x05d8 */ 60*4882a593Smuzhiyun uint32_t top_pvtpll_con[4]; /* address offset: 0x0600 */ 61*4882a593Smuzhiyun uint32_t top_pvtpll_status[2]; /* address offset: 0x0610 */ 62*4882a593Smuzhiyun uint32_t reserved13[(0x0620 - 0x0610) / 4 - 2]; /* address offset: 0x0618 */ 63*4882a593Smuzhiyun uint32_t cpu_pvtpll_con[4]; /* address offset: 0x0620 */ 64*4882a593Smuzhiyun uint32_t cpu_pvtpll_status[2]; /* address offset: 0x0630 */ 65*4882a593Smuzhiyun uint32_t reserved14[(0x0640 - 0x0630) / 4 - 2]; /* address offset: 0x0638 */ 66*4882a593Smuzhiyun uint32_t gpu_pvtpll_con[4]; /* address offset: 0x0640 */ 67*4882a593Smuzhiyun uint32_t gpu_pvtpll_status[2]; /* address offset: 0x0650 */ 68*4882a593Smuzhiyun uint32_t reserved15[(0x0660 - 0x0650) / 4 - 2]; /* address offset: 0x0658 */ 69*4882a593Smuzhiyun uint32_t npu_pvtpll_con[4]; /* address offset: 0x0660 */ 70*4882a593Smuzhiyun uint32_t npu_pvtpll_status[2]; /* address offset: 0x0670 */ 71*4882a593Smuzhiyun uint32_t reserved16[(0x0800 - 0x0670) / 4 - 2]; /* address offset: 0x0678 */ 72*4882a593Smuzhiyun uint32_t chip_id; /* address offset: 0x0800 */ 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun check_member(rk3562_grf, chip_id, 0x0800); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77