1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_GRF_RK3528_H 7*4882a593Smuzhiyun #define _ASM_ARCH_GRF_RK3528_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3528_grf { 12*4882a593Smuzhiyun uint32_t reserved0[0x40018 / 4]; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* vpugrf*/ 15*4882a593Smuzhiyun uint32_t gmac1_con0; /* Address Offset: 0x40018 */ 16*4882a593Smuzhiyun uint32_t gmac1_con1; /* Address Offset: 0x4001c */ 17*4882a593Smuzhiyun uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1]; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* vogrf */ 20*4882a593Smuzhiyun uint32_t gmac0_con; /* Address Offset: 0x60018 */ 21*4882a593Smuzhiyun uint32_t macphy_con0; /* Address Offset: 0x6001c */ 22*4882a593Smuzhiyun uint32_t macphy_con1; /* Address Offset: 0x60020 */ 23*4882a593Smuzhiyun uint32_t sdmmc_con0; /* Address Offset: 0x60024 */ 24*4882a593Smuzhiyun uint32_t sdmmc_con1; /* Address Offset: 0x60028 */ 25*4882a593Smuzhiyun uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1]; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* pmugrf */ 28*4882a593Smuzhiyun uint32_t soc_con[8]; /* Address Offset: 0x70000 */ 29*4882a593Smuzhiyun uint32_t soc_status; /* Address Offset: 0x70020 */ 30*4882a593Smuzhiyun uint32_t reserved3[3]; /* Address Offset: 0x70024 */ 31*4882a593Smuzhiyun uint32_t pmuio_vsel; /* Address Offset: 0x70030 */ 32*4882a593Smuzhiyun uint32_t reserved4[3]; /* Address Offset: 0x70034 */ 33*4882a593Smuzhiyun uint32_t mem_con; /* Address Offset: 0x70040 */ 34*4882a593Smuzhiyun uint32_t reserved5[47]; /* Address Offset: 0x70044 */ 35*4882a593Smuzhiyun uint32_t rstfunc_status; /* Address Offset: 0x70100 */ 36*4882a593Smuzhiyun uint32_t rstfunc_clr; /* Address Offset: 0x70104 */ 37*4882a593Smuzhiyun uint32_t reserved6[62]; /* Address Offset: 0x70108 */ 38*4882a593Smuzhiyun uint32_t os_reg0; /* Address Offset: 0x70200 */ 39*4882a593Smuzhiyun uint32_t os_reg1; /* Address Offset: 0x70204 */ 40*4882a593Smuzhiyun uint32_t os_reg2; /* Address Offset: 0x70208 */ 41*4882a593Smuzhiyun uint32_t os_reg3; /* Address Offset: 0x7020C */ 42*4882a593Smuzhiyun uint32_t os_reg4; /* Address Offset: 0x70210 */ 43*4882a593Smuzhiyun uint32_t os_reg5; /* Address Offset: 0x70214 */ 44*4882a593Smuzhiyun uint32_t os_reg6; /* Address Offset: 0x70218 */ 45*4882a593Smuzhiyun uint32_t os_reg7; /* Address Offset: 0x7021C */ 46*4882a593Smuzhiyun uint32_t os_reg8; /* Address Offset: 0x70220 */ 47*4882a593Smuzhiyun uint32_t os_reg9; /* Address Offset: 0x70224 */ 48*4882a593Smuzhiyun uint32_t os_reg10; /* Address Offset: 0x70228 */ 49*4882a593Smuzhiyun uint32_t os_reg11; /* Address Offset: 0x7022C */ 50*4882a593Smuzhiyun uint32_t os_reg12; /* Address Offset: 0x70230 */ 51*4882a593Smuzhiyun uint32_t os_reg13; /* Address Offset: 0x70234 */ 52*4882a593Smuzhiyun uint32_t os_reg14; /* Address Offset: 0x70238 */ 53*4882a593Smuzhiyun uint32_t os_reg15; /* Address Offset: 0x7023C */ 54*4882a593Smuzhiyun uint32_t os_reg16; /* Address Offset: 0x70240 */ 55*4882a593Smuzhiyun uint32_t os_reg17; /* Address Offset: 0x70244 */ 56*4882a593Smuzhiyun uint32_t os_reg18; /* Address Offset: 0x70248 */ 57*4882a593Smuzhiyun uint32_t os_reg19; /* Address Offset: 0x7024C */ 58*4882a593Smuzhiyun uint32_t os_reg20; /* Address Offset: 0x70250 */ 59*4882a593Smuzhiyun uint32_t os_reg21; /* Address Offset: 0x70254 */ 60*4882a593Smuzhiyun uint32_t os_reg22; /* Address Offset: 0x70258 */ 61*4882a593Smuzhiyun uint32_t os_reg23; /* Address Offset: 0x7025C */ 62*4882a593Smuzhiyun uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1]; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */ 65*4882a593Smuzhiyun uint32_t reserved8[2]; /* Address Offset: 0x80008 */ 66*4882a593Smuzhiyun uint32_t grf_sys_status; /* Address Offset: 0x80010 */ 67*4882a593Smuzhiyun uint32_t reserved9[3]; /* Address Offset: 0x80014 */ 68*4882a593Smuzhiyun uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */ 69*4882a593Smuzhiyun uint32_t reserved10[2]; /* Address Offset: 0x80028 */ 70*4882a593Smuzhiyun uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */ 71*4882a593Smuzhiyun uint32_t reserved11[17]; /* Address Offset: 0x8003C */ 72*4882a593Smuzhiyun uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */ 73*4882a593Smuzhiyun uint32_t reserved12[59]; /* Address Offset: 0x80094 */ 74*4882a593Smuzhiyun uint32_t grf_soc_code; /* Address Offset: 0x80180 */ 75*4882a593Smuzhiyun uint32_t reserved13[3]; /* Address Offset: 0x80184 */ 76*4882a593Smuzhiyun uint32_t grf_soc_version; /* Address Offset: 0x80190 */ 77*4882a593Smuzhiyun uint32_t reserved14[3]; /* Address Offset: 0x80194 */ 78*4882a593Smuzhiyun uint32_t grf_chip_id; /* Address Offset: 0x801A0 */ 79*4882a593Smuzhiyun uint32_t reserved15[3]; /* Address Offset: 0x801A4 */ 80*4882a593Smuzhiyun uint32_t grf_chip_version; /* Address Offset: 0x801B0 */ 81*4882a593Smuzhiyun uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1]; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun check_member(rk3528_grf, sdmmc_con1, 0x60028); 86*4882a593Smuzhiyun check_member(rk3528_grf, os_reg23, 0x7025C); 87*4882a593Smuzhiyun check_member(rk3528_grf, grf_chip_version, 0x801B0); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90