1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_GRF_RK3368_H 8*4882a593Smuzhiyun #define _ASM_ARCH_GRF_RK3368_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rk3368_grf { 13*4882a593Smuzhiyun u32 gpio1a_iomux; 14*4882a593Smuzhiyun u32 gpio1b_iomux; 15*4882a593Smuzhiyun u32 gpio1c_iomux; 16*4882a593Smuzhiyun u32 gpio1d_iomux; 17*4882a593Smuzhiyun u32 gpio2a_iomux; 18*4882a593Smuzhiyun u32 gpio2b_iomux; 19*4882a593Smuzhiyun u32 gpio2c_iomux; 20*4882a593Smuzhiyun u32 gpio2d_iomux; 21*4882a593Smuzhiyun u32 gpio3a_iomux; 22*4882a593Smuzhiyun u32 gpio3b_iomux; 23*4882a593Smuzhiyun u32 gpio3c_iomux; 24*4882a593Smuzhiyun u32 gpio3d_iomux; 25*4882a593Smuzhiyun u32 reserved[0x34]; 26*4882a593Smuzhiyun u32 gpio1a_pull; 27*4882a593Smuzhiyun u32 gpio1b_pull; 28*4882a593Smuzhiyun u32 gpio1c_pull; 29*4882a593Smuzhiyun u32 gpio1d_pull; 30*4882a593Smuzhiyun u32 gpio2a_pull; 31*4882a593Smuzhiyun u32 gpio2b_pull; 32*4882a593Smuzhiyun u32 gpio2c_pull; 33*4882a593Smuzhiyun u32 gpio2d_pull; 34*4882a593Smuzhiyun u32 gpio3a_pull; 35*4882a593Smuzhiyun u32 gpio3b_pull; 36*4882a593Smuzhiyun u32 gpio3c_pull; 37*4882a593Smuzhiyun u32 gpio3d_pull; 38*4882a593Smuzhiyun u32 reserved1[0x34]; 39*4882a593Smuzhiyun u32 gpio1a_drv; 40*4882a593Smuzhiyun u32 gpio1b_drv; 41*4882a593Smuzhiyun u32 gpio1c_drv; 42*4882a593Smuzhiyun u32 gpio1d_drv; 43*4882a593Smuzhiyun u32 gpio2a_drv; 44*4882a593Smuzhiyun u32 gpio2b_drv; 45*4882a593Smuzhiyun u32 gpio2c_drv; 46*4882a593Smuzhiyun u32 gpio2d_drv; 47*4882a593Smuzhiyun u32 gpio3a_drv; 48*4882a593Smuzhiyun u32 gpio3b_drv; 49*4882a593Smuzhiyun u32 gpio3c_drv; 50*4882a593Smuzhiyun u32 gpio3d_drv; 51*4882a593Smuzhiyun u32 reserved2[0x34]; 52*4882a593Smuzhiyun u32 gpio1l_sr; 53*4882a593Smuzhiyun u32 gpio1h_sr; 54*4882a593Smuzhiyun u32 gpio2l_sr; 55*4882a593Smuzhiyun u32 gpio2h_sr; 56*4882a593Smuzhiyun u32 gpio3l_sr; 57*4882a593Smuzhiyun u32 gpio3h_sr; 58*4882a593Smuzhiyun u32 reserved3[0x1a]; 59*4882a593Smuzhiyun u32 gpio_smt; 60*4882a593Smuzhiyun u32 reserved4[0x1f]; 61*4882a593Smuzhiyun u32 soc_con0; 62*4882a593Smuzhiyun u32 soc_con1; 63*4882a593Smuzhiyun u32 soc_con2; 64*4882a593Smuzhiyun u32 soc_con3; 65*4882a593Smuzhiyun u32 soc_con4; 66*4882a593Smuzhiyun u32 soc_con5; 67*4882a593Smuzhiyun u32 soc_con6; 68*4882a593Smuzhiyun u32 soc_con7; 69*4882a593Smuzhiyun u32 soc_con8; 70*4882a593Smuzhiyun u32 soc_con9; 71*4882a593Smuzhiyun u32 soc_con10; 72*4882a593Smuzhiyun u32 soc_con11; 73*4882a593Smuzhiyun u32 soc_con12; 74*4882a593Smuzhiyun u32 soc_con13; 75*4882a593Smuzhiyun u32 soc_con14; 76*4882a593Smuzhiyun u32 soc_con15; 77*4882a593Smuzhiyun u32 soc_con16; 78*4882a593Smuzhiyun u32 soc_con17; 79*4882a593Smuzhiyun u32 reserved5[0x6e]; 80*4882a593Smuzhiyun u32 ddrc0_con0; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun check_member(rk3368_grf, soc_con17, 0x444); 83*4882a593Smuzhiyun check_member(rk3368_grf, ddrc0_con0, 0x600); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct rk3368_pmu_grf { 86*4882a593Smuzhiyun u32 gpio0a_iomux; 87*4882a593Smuzhiyun u32 gpio0b_iomux; 88*4882a593Smuzhiyun u32 gpio0c_iomux; 89*4882a593Smuzhiyun u32 gpio0d_iomux; 90*4882a593Smuzhiyun u32 gpio0a_pull; 91*4882a593Smuzhiyun u32 gpio0b_pull; 92*4882a593Smuzhiyun u32 gpio0c_pull; 93*4882a593Smuzhiyun u32 gpio0d_pull; 94*4882a593Smuzhiyun u32 gpio0a_drv; 95*4882a593Smuzhiyun u32 gpio0b_drv; 96*4882a593Smuzhiyun u32 gpio0c_drv; 97*4882a593Smuzhiyun u32 gpio0d_drv; 98*4882a593Smuzhiyun u32 gpio0l_sr; 99*4882a593Smuzhiyun u32 gpio0h_sr; 100*4882a593Smuzhiyun u32 reserved[0x72]; 101*4882a593Smuzhiyun u32 os_reg[4]; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); 104*4882a593Smuzhiyun check_member(rk3368_pmu_grf, os_reg[0], 0x200); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /*GRF_SOC_CON11/12/13*/ 107*4882a593Smuzhiyun enum { 108*4882a593Smuzhiyun MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, 109*4882a593Smuzhiyun MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /*GRF_SOC_CON12*/ 113*4882a593Smuzhiyun enum { 114*4882a593Smuzhiyun MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, 115*4882a593Smuzhiyun MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /*GRF_SOC_CON13*/ 119*4882a593Smuzhiyun enum { 120*4882a593Smuzhiyun MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, 121*4882a593Smuzhiyun MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /*GRF_SOC_CON14*/ 125*4882a593Smuzhiyun enum { 126*4882a593Smuzhiyun MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, 127*4882a593Smuzhiyun MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), 128*4882a593Smuzhiyun MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, 129*4882a593Smuzhiyun MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), 130*4882a593Smuzhiyun MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, 131*4882a593Smuzhiyun MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), 132*4882a593Smuzhiyun MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, 133*4882a593Smuzhiyun MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137