1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ 8*4882a593Smuzhiyun #define __SOC_ROCKCHIP_RK3328_GRF_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct rk3328_grf_regs { 11*4882a593Smuzhiyun u32 gpio0a_iomux; 12*4882a593Smuzhiyun u32 gpio0b_iomux; 13*4882a593Smuzhiyun u32 gpio0c_iomux; 14*4882a593Smuzhiyun u32 gpio0d_iomux; 15*4882a593Smuzhiyun u32 gpio1a_iomux; 16*4882a593Smuzhiyun u32 gpio1b_iomux; 17*4882a593Smuzhiyun u32 gpio1c_iomux; 18*4882a593Smuzhiyun u32 gpio1d_iomux; 19*4882a593Smuzhiyun u32 gpio2a_iomux; 20*4882a593Smuzhiyun u32 gpio2bl_iomux; 21*4882a593Smuzhiyun u32 gpio2bh_iomux; 22*4882a593Smuzhiyun u32 gpio2cl_iomux; 23*4882a593Smuzhiyun u32 gpio2ch_iomux; 24*4882a593Smuzhiyun u32 gpio2d_iomux; 25*4882a593Smuzhiyun u32 gpio3al_iomux; 26*4882a593Smuzhiyun u32 gpio3ah_iomux; 27*4882a593Smuzhiyun u32 gpio3bl_iomux; 28*4882a593Smuzhiyun u32 gpio3bh_iomux; 29*4882a593Smuzhiyun u32 gpio3c_iomux; 30*4882a593Smuzhiyun u32 gpio3d_iomux; 31*4882a593Smuzhiyun u32 com_iomux; 32*4882a593Smuzhiyun u32 reserved1[(0x100 - 0x54) / 4]; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun u32 gpio0a_p; 35*4882a593Smuzhiyun u32 gpio0b_p; 36*4882a593Smuzhiyun u32 gpio0c_p; 37*4882a593Smuzhiyun u32 gpio0d_p; 38*4882a593Smuzhiyun u32 gpio1a_p; 39*4882a593Smuzhiyun u32 gpio1b_p; 40*4882a593Smuzhiyun u32 gpio1c_p; 41*4882a593Smuzhiyun u32 gpio1d_p; 42*4882a593Smuzhiyun u32 gpio2a_p; 43*4882a593Smuzhiyun u32 gpio2b_p; 44*4882a593Smuzhiyun u32 gpio2c_p; 45*4882a593Smuzhiyun u32 gpio2d_p; 46*4882a593Smuzhiyun u32 gpio3a_p; 47*4882a593Smuzhiyun u32 gpio3b_p; 48*4882a593Smuzhiyun u32 gpio3c_p; 49*4882a593Smuzhiyun u32 gpio3d_p; 50*4882a593Smuzhiyun u32 reserved2[(0x200 - 0x140) / 4]; 51*4882a593Smuzhiyun u32 gpio0a_e; 52*4882a593Smuzhiyun u32 gpio0b_e; 53*4882a593Smuzhiyun u32 gpio0c_e; 54*4882a593Smuzhiyun u32 gpio0d_e; 55*4882a593Smuzhiyun u32 gpio1a_e; 56*4882a593Smuzhiyun u32 gpio1b_e; 57*4882a593Smuzhiyun u32 gpio1c_e; 58*4882a593Smuzhiyun u32 gpio1d_e; 59*4882a593Smuzhiyun u32 gpio2a_e; 60*4882a593Smuzhiyun u32 gpio2b_e; 61*4882a593Smuzhiyun u32 gpio2c_e; 62*4882a593Smuzhiyun u32 gpio2d_e; 63*4882a593Smuzhiyun u32 gpio3a_e; 64*4882a593Smuzhiyun u32 gpio3b_e; 65*4882a593Smuzhiyun u32 gpio3c_e; 66*4882a593Smuzhiyun u32 gpio3d_e; 67*4882a593Smuzhiyun u32 reserved3[(0x300 - 0x240) / 4]; 68*4882a593Smuzhiyun u32 gpio0l_sr; 69*4882a593Smuzhiyun u32 gpio0h_sr; 70*4882a593Smuzhiyun u32 gpio1l_sr; 71*4882a593Smuzhiyun u32 gpio1h_sr; 72*4882a593Smuzhiyun u32 gpio2l_sr; 73*4882a593Smuzhiyun u32 gpio2h_sr; 74*4882a593Smuzhiyun u32 gpio3l_sr; 75*4882a593Smuzhiyun u32 gpio3h_sr; 76*4882a593Smuzhiyun u32 reserved4[(0x380 - 0x320) / 4]; 77*4882a593Smuzhiyun u32 gpio0l_smt; 78*4882a593Smuzhiyun u32 gpio0h_smt; 79*4882a593Smuzhiyun u32 gpio1l_smt; 80*4882a593Smuzhiyun u32 gpio1h_smt; 81*4882a593Smuzhiyun u32 gpio2l_smt; 82*4882a593Smuzhiyun u32 gpio2h_smt; 83*4882a593Smuzhiyun u32 gpio3l_smt; 84*4882a593Smuzhiyun u32 gpio3h_smt; 85*4882a593Smuzhiyun u32 reserved5[(0x400 - 0x3a0) / 4]; 86*4882a593Smuzhiyun u32 soc_con[11]; 87*4882a593Smuzhiyun u32 reserved6[(0x480 - 0x42c) / 4]; 88*4882a593Smuzhiyun u32 soc_status[5]; 89*4882a593Smuzhiyun u32 reserved7[(0x4c0 - 0x494) / 4]; 90*4882a593Smuzhiyun u32 otg3_con[2]; 91*4882a593Smuzhiyun u32 reserved8[(0x500 - 0x4c8) / 4]; 92*4882a593Smuzhiyun u32 cpu_con[2]; 93*4882a593Smuzhiyun u32 reserved9[(0x520 - 0x508) / 4]; 94*4882a593Smuzhiyun u32 cpu_status[2]; 95*4882a593Smuzhiyun u32 reserved10[(0x5c8 - 0x528) / 4]; 96*4882a593Smuzhiyun u32 os_reg[8]; 97*4882a593Smuzhiyun u32 reserved11[(0x680 - 0x5e8) / 4]; 98*4882a593Smuzhiyun u32 sig_detect_con; 99*4882a593Smuzhiyun u32 reserved12[3]; 100*4882a593Smuzhiyun u32 sig_detect_status; 101*4882a593Smuzhiyun u32 reserved13[3]; 102*4882a593Smuzhiyun u32 sig_detect_status_clr; 103*4882a593Smuzhiyun u32 reserved14[3]; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun u32 sdmmc_det_counter; 106*4882a593Smuzhiyun u32 reserved15[(0x700 - 0x6b4) / 4]; 107*4882a593Smuzhiyun u32 host0_con[3]; 108*4882a593Smuzhiyun u32 reserved16[(0x880 - 0x70c) / 4]; 109*4882a593Smuzhiyun u32 otg_con0; 110*4882a593Smuzhiyun u32 reserved17[3]; 111*4882a593Smuzhiyun u32 host0_status; 112*4882a593Smuzhiyun u32 reserved18[(0x900 - 0x894) / 4]; 113*4882a593Smuzhiyun u32 mac_con[3]; 114*4882a593Smuzhiyun u32 reserved19[(0xb00 - 0x90c) / 4]; 115*4882a593Smuzhiyun u32 macphy_con[4]; 116*4882a593Smuzhiyun u32 macphy_status; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun check_member(rk3328_grf_regs, macphy_status, 0xb10); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct rk3328_sgrf_regs { 121*4882a593Smuzhiyun u32 soc_con[6]; 122*4882a593Smuzhiyun u32 reserved0[(0x100 - 0x18) / 4]; 123*4882a593Smuzhiyun u32 dmac_con[6]; 124*4882a593Smuzhiyun u32 reserved1[(0x180 - 0x118) / 4]; 125*4882a593Smuzhiyun u32 fast_boot_addr; 126*4882a593Smuzhiyun u32 reserved2[(0x200 - 0x184) / 4]; 127*4882a593Smuzhiyun u32 chip_fuse_con; 128*4882a593Smuzhiyun u32 reserved3[(0x280 - 0x204) / 4]; 129*4882a593Smuzhiyun u32 hdcp_key_reg[8]; 130*4882a593Smuzhiyun u32 hdcp_key_access_mask; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ 136