1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Google, Inc 3*4882a593Smuzhiyun * Copyright 2014 Rockchip Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_GRF_RK3288_H 9*4882a593Smuzhiyun #define _ASM_ARCH_GRF_RK3288_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3288_grf_gpio_lh { 12*4882a593Smuzhiyun u32 l; 13*4882a593Smuzhiyun u32 h; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct rk3288_grf { 17*4882a593Smuzhiyun u32 reserved[3]; 18*4882a593Smuzhiyun u32 gpio1d_iomux; 19*4882a593Smuzhiyun u32 gpio2a_iomux; 20*4882a593Smuzhiyun u32 gpio2b_iomux; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun u32 gpio2c_iomux; 23*4882a593Smuzhiyun u32 reserved2; 24*4882a593Smuzhiyun u32 gpio3a_iomux; 25*4882a593Smuzhiyun u32 gpio3b_iomux; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u32 gpio3c_iomux; 28*4882a593Smuzhiyun u32 gpio3dl_iomux; 29*4882a593Smuzhiyun u32 gpio3dh_iomux; 30*4882a593Smuzhiyun u32 gpio4al_iomux; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u32 gpio4ah_iomux; 33*4882a593Smuzhiyun u32 gpio4bl_iomux; 34*4882a593Smuzhiyun u32 reserved3; 35*4882a593Smuzhiyun u32 gpio4c_iomux; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u32 gpio4d_iomux; 38*4882a593Smuzhiyun u32 reserved4; 39*4882a593Smuzhiyun u32 gpio5b_iomux; 40*4882a593Smuzhiyun u32 gpio5c_iomux; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u32 reserved5; 43*4882a593Smuzhiyun u32 gpio6a_iomux; 44*4882a593Smuzhiyun u32 gpio6b_iomux; 45*4882a593Smuzhiyun u32 gpio6c_iomux; 46*4882a593Smuzhiyun u32 reserved6; 47*4882a593Smuzhiyun u32 gpio7a_iomux; 48*4882a593Smuzhiyun u32 gpio7b_iomux; 49*4882a593Smuzhiyun u32 gpio7cl_iomux; 50*4882a593Smuzhiyun u32 gpio7ch_iomux; 51*4882a593Smuzhiyun u32 reserved7; 52*4882a593Smuzhiyun u32 gpio8a_iomux; 53*4882a593Smuzhiyun u32 gpio8b_iomux; 54*4882a593Smuzhiyun u32 reserved8[30]; 55*4882a593Smuzhiyun struct rk3288_grf_gpio_lh gpio_sr[8]; 56*4882a593Smuzhiyun u32 gpio1_p[8][4]; 57*4882a593Smuzhiyun u32 gpio1_e[8][4]; 58*4882a593Smuzhiyun u32 gpio_smt; 59*4882a593Smuzhiyun u32 soc_con0; 60*4882a593Smuzhiyun u32 soc_con1; 61*4882a593Smuzhiyun u32 soc_con2; 62*4882a593Smuzhiyun u32 soc_con3; 63*4882a593Smuzhiyun u32 soc_con4; 64*4882a593Smuzhiyun u32 soc_con5; 65*4882a593Smuzhiyun u32 soc_con6; 66*4882a593Smuzhiyun u32 soc_con7; 67*4882a593Smuzhiyun u32 soc_con8; 68*4882a593Smuzhiyun u32 soc_con9; 69*4882a593Smuzhiyun u32 soc_con10; 70*4882a593Smuzhiyun u32 soc_con11; 71*4882a593Smuzhiyun u32 soc_con12; 72*4882a593Smuzhiyun u32 soc_con13; 73*4882a593Smuzhiyun u32 soc_con14; 74*4882a593Smuzhiyun u32 soc_status[22]; 75*4882a593Smuzhiyun u32 reserved9[2]; 76*4882a593Smuzhiyun u32 peridmac_con[4]; 77*4882a593Smuzhiyun u32 ddrc0_con0; 78*4882a593Smuzhiyun u32 ddrc1_con0; 79*4882a593Smuzhiyun u32 cpu_con[5]; 80*4882a593Smuzhiyun u32 reserved10[3]; 81*4882a593Smuzhiyun u32 cpu_status0; 82*4882a593Smuzhiyun u32 reserved11; 83*4882a593Smuzhiyun u32 uoc0_con[5]; 84*4882a593Smuzhiyun u32 uoc1_con[5]; 85*4882a593Smuzhiyun u32 uoc2_con[4]; 86*4882a593Smuzhiyun u32 uoc3_con[2]; 87*4882a593Smuzhiyun u32 uoc4_con[2]; 88*4882a593Smuzhiyun u32 pvtm_con[3]; 89*4882a593Smuzhiyun u32 pvtm_status[3]; 90*4882a593Smuzhiyun u32 io_vsel; 91*4882a593Smuzhiyun u32 saradc_testbit; 92*4882a593Smuzhiyun u32 tsadc_testbit_l; 93*4882a593Smuzhiyun u32 tsadc_testbit_h; 94*4882a593Smuzhiyun u32 os_reg[4]; 95*4882a593Smuzhiyun u32 reserved12; 96*4882a593Smuzhiyun u32 soc_con15; 97*4882a593Smuzhiyun u32 soc_con16; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct rk3288_sgrf { 101*4882a593Smuzhiyun u32 soc_con0; 102*4882a593Smuzhiyun u32 soc_con1; 103*4882a593Smuzhiyun u32 soc_con2; 104*4882a593Smuzhiyun u32 soc_con3; 105*4882a593Smuzhiyun u32 soc_con4; 106*4882a593Smuzhiyun u32 soc_con5; 107*4882a593Smuzhiyun u32 reserved1[(0x20-0x18)/4]; 108*4882a593Smuzhiyun u32 busdmac_con[2]; 109*4882a593Smuzhiyun u32 reserved2[(0x40-0x28)/4]; 110*4882a593Smuzhiyun u32 cpu_con[3]; 111*4882a593Smuzhiyun u32 reserved3[(0x50-0x4c)/4]; 112*4882a593Smuzhiyun u32 soc_con6; 113*4882a593Smuzhiyun u32 soc_con7; 114*4882a593Smuzhiyun u32 soc_con8; 115*4882a593Smuzhiyun u32 soc_con9; 116*4882a593Smuzhiyun u32 soc_con10; 117*4882a593Smuzhiyun u32 soc_con11; 118*4882a593Smuzhiyun u32 soc_con12; 119*4882a593Smuzhiyun u32 soc_con13; 120*4882a593Smuzhiyun u32 soc_con14; 121*4882a593Smuzhiyun u32 soc_con15; 122*4882a593Smuzhiyun u32 soc_con16; 123*4882a593Smuzhiyun u32 soc_con17; 124*4882a593Smuzhiyun u32 soc_con18; 125*4882a593Smuzhiyun u32 soc_con19; 126*4882a593Smuzhiyun u32 soc_con20; 127*4882a593Smuzhiyun u32 soc_con21; 128*4882a593Smuzhiyun u32 reserved4[(0x100-0x90)/4]; 129*4882a593Smuzhiyun u32 soc_status[2]; 130*4882a593Smuzhiyun u32 reserved5[(0x120-0x108)/4]; 131*4882a593Smuzhiyun u32 fast_boot_addr; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* GRF_GPIO1D_IOMUX */ 135*4882a593Smuzhiyun enum { 136*4882a593Smuzhiyun GPIO1D3_SHIFT = 6, 137*4882a593Smuzhiyun GPIO1D3_MASK = 1, 138*4882a593Smuzhiyun GPIO1D3_GPIO = 0, 139*4882a593Smuzhiyun GPIO1D3_LCDC0_DCLK, 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun GPIO1D2_SHIFT = 4, 142*4882a593Smuzhiyun GPIO1D2_MASK = 1, 143*4882a593Smuzhiyun GPIO1D2_GPIO = 0, 144*4882a593Smuzhiyun GPIO1D2_LCDC0_DEN, 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun GPIO1D1_SHIFT = 2, 147*4882a593Smuzhiyun GPIO1D1_MASK = 1, 148*4882a593Smuzhiyun GPIO1D1_GPIO = 0, 149*4882a593Smuzhiyun GPIO1D1_LCDC0_VSYNC, 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun GPIO1D0_SHIFT = 0, 152*4882a593Smuzhiyun GPIO1D0_MASK = 1, 153*4882a593Smuzhiyun GPIO1D0_GPIO = 0, 154*4882a593Smuzhiyun GPIO1D0_LCDC0_HSYNC, 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* GRF_GPIO2C_IOMUX */ 158*4882a593Smuzhiyun enum { 159*4882a593Smuzhiyun GPIO2C1_SHIFT = 2, 160*4882a593Smuzhiyun GPIO2C1_MASK = 1, 161*4882a593Smuzhiyun GPIO2C1_GPIO = 0, 162*4882a593Smuzhiyun GPIO2C1_I2C3CAM_SDA, 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun GPIO2C0_SHIFT = 0, 165*4882a593Smuzhiyun GPIO2C0_MASK = 1, 166*4882a593Smuzhiyun GPIO2C0_GPIO = 0, 167*4882a593Smuzhiyun GPIO2C0_I2C3CAM_SCL, 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* GRF_GPIO3A_IOMUX */ 171*4882a593Smuzhiyun enum { 172*4882a593Smuzhiyun GPIO3A7_SHIFT = 14, 173*4882a593Smuzhiyun GPIO3A7_MASK = 3, 174*4882a593Smuzhiyun GPIO3A7_GPIO = 0, 175*4882a593Smuzhiyun GPIO3A7_FLASH0_DATA7, 176*4882a593Smuzhiyun GPIO3A7_EMMC_DATA7, 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun GPIO3A6_SHIFT = 12, 179*4882a593Smuzhiyun GPIO3A6_MASK = 3, 180*4882a593Smuzhiyun GPIO3A6_GPIO = 0, 181*4882a593Smuzhiyun GPIO3A6_FLASH0_DATA6, 182*4882a593Smuzhiyun GPIO3A6_EMMC_DATA6, 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun GPIO3A5_SHIFT = 10, 185*4882a593Smuzhiyun GPIO3A5_MASK = 3, 186*4882a593Smuzhiyun GPIO3A5_GPIO = 0, 187*4882a593Smuzhiyun GPIO3A5_FLASH0_DATA5, 188*4882a593Smuzhiyun GPIO3A5_EMMC_DATA5, 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun GPIO3A4_SHIFT = 8, 191*4882a593Smuzhiyun GPIO3A4_MASK = 3, 192*4882a593Smuzhiyun GPIO3A4_GPIO = 0, 193*4882a593Smuzhiyun GPIO3A4_FLASH0_DATA4, 194*4882a593Smuzhiyun GPIO3A4_EMMC_DATA4, 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun GPIO3A3_SHIFT = 6, 197*4882a593Smuzhiyun GPIO3A3_MASK = 3, 198*4882a593Smuzhiyun GPIO3A3_GPIO = 0, 199*4882a593Smuzhiyun GPIO3A3_FLASH0_DATA3, 200*4882a593Smuzhiyun GPIO3A3_EMMC_DATA3, 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun GPIO3A2_SHIFT = 4, 203*4882a593Smuzhiyun GPIO3A2_MASK = 3, 204*4882a593Smuzhiyun GPIO3A2_GPIO = 0, 205*4882a593Smuzhiyun GPIO3A2_FLASH0_DATA2, 206*4882a593Smuzhiyun GPIO3A2_EMMC_DATA2, 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun GPIO3A1_SHIFT = 2, 209*4882a593Smuzhiyun GPIO3A1_MASK = 3, 210*4882a593Smuzhiyun GPIO3A1_GPIO = 0, 211*4882a593Smuzhiyun GPIO3A1_FLASH0_DATA1, 212*4882a593Smuzhiyun GPIO3A1_EMMC_DATA1, 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun GPIO3A0_SHIFT = 0, 215*4882a593Smuzhiyun GPIO3A0_MASK = 3, 216*4882a593Smuzhiyun GPIO3A0_GPIO = 0, 217*4882a593Smuzhiyun GPIO3A0_FLASH0_DATA0, 218*4882a593Smuzhiyun GPIO3A0_EMMC_DATA0, 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* GRF_GPIO3B_IOMUX */ 222*4882a593Smuzhiyun enum { 223*4882a593Smuzhiyun GPIO3B7_SHIFT = 14, 224*4882a593Smuzhiyun GPIO3B7_MASK = 1, 225*4882a593Smuzhiyun GPIO3B7_GPIO = 0, 226*4882a593Smuzhiyun GPIO3B7_FLASH0_CSN1, 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun GPIO3B6_SHIFT = 12, 229*4882a593Smuzhiyun GPIO3B6_MASK = 1, 230*4882a593Smuzhiyun GPIO3B6_GPIO = 0, 231*4882a593Smuzhiyun GPIO3B6_FLASH0_CSN0, 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun GPIO3B5_SHIFT = 10, 234*4882a593Smuzhiyun GPIO3B5_MASK = 1, 235*4882a593Smuzhiyun GPIO3B5_GPIO = 0, 236*4882a593Smuzhiyun GPIO3B5_FLASH0_WRN, 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun GPIO3B4_SHIFT = 8, 239*4882a593Smuzhiyun GPIO3B4_MASK = 1, 240*4882a593Smuzhiyun GPIO3B4_GPIO = 0, 241*4882a593Smuzhiyun GPIO3B4_FLASH0_CLE, 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun GPIO3B3_SHIFT = 6, 244*4882a593Smuzhiyun GPIO3B3_MASK = 1, 245*4882a593Smuzhiyun GPIO3B3_GPIO = 0, 246*4882a593Smuzhiyun GPIO3B3_FLASH0_ALE, 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun GPIO3B2_SHIFT = 4, 249*4882a593Smuzhiyun GPIO3B2_MASK = 1, 250*4882a593Smuzhiyun GPIO3B2_GPIO = 0, 251*4882a593Smuzhiyun GPIO3B2_FLASH0_RDN, 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun GPIO3B1_SHIFT = 2, 254*4882a593Smuzhiyun GPIO3B1_MASK = 3, 255*4882a593Smuzhiyun GPIO3B1_GPIO = 0, 256*4882a593Smuzhiyun GPIO3B1_FLASH0_WP, 257*4882a593Smuzhiyun GPIO3B1_EMMC_PWREN, 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun GPIO3B0_SHIFT = 0, 260*4882a593Smuzhiyun GPIO3B0_MASK = 1, 261*4882a593Smuzhiyun GPIO3B0_GPIO = 0, 262*4882a593Smuzhiyun GPIO3B0_FLASH0_RDY, 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun /* GRF_GPIO3C_IOMUX */ 266*4882a593Smuzhiyun enum { 267*4882a593Smuzhiyun GPIO3C2_SHIFT = 4, 268*4882a593Smuzhiyun GPIO3C2_MASK = 3, 269*4882a593Smuzhiyun GPIO3C2_GPIO = 0, 270*4882a593Smuzhiyun GPIO3C2_FLASH0_DQS, 271*4882a593Smuzhiyun GPIO3C2_EMMC_CLKOUT, 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun GPIO3C1_SHIFT = 2, 274*4882a593Smuzhiyun GPIO3C1_MASK = 3, 275*4882a593Smuzhiyun GPIO3C1_GPIO = 0, 276*4882a593Smuzhiyun GPIO3C1_FLASH0_CSN3, 277*4882a593Smuzhiyun GPIO3C1_EMMC_RSTNOUT, 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun GPIO3C0_SHIFT = 0, 280*4882a593Smuzhiyun GPIO3C0_MASK = 3, 281*4882a593Smuzhiyun GPIO3C0_GPIO = 0, 282*4882a593Smuzhiyun GPIO3C0_FLASH0_CSN2, 283*4882a593Smuzhiyun GPIO3C0_EMMC_CMD, 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* GRF_GPIO3DL_IOMUX */ 287*4882a593Smuzhiyun enum { 288*4882a593Smuzhiyun GPIO3D3_SHIFT = 12, 289*4882a593Smuzhiyun GPIO3D3_MASK = 7, 290*4882a593Smuzhiyun GPIO3D3_GPIO = 0, 291*4882a593Smuzhiyun GPIO3D3_FLASH1_DATA3, 292*4882a593Smuzhiyun GPIO3D3_HOST_DOUT3, 293*4882a593Smuzhiyun GPIO3D3_MAC_RXD3, 294*4882a593Smuzhiyun GPIO3D3_SDIO1_DATA3, 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun GPIO3D2_SHIFT = 8, 297*4882a593Smuzhiyun GPIO3D2_MASK = 7, 298*4882a593Smuzhiyun GPIO3D2_GPIO = 0, 299*4882a593Smuzhiyun GPIO3D2_FLASH1_DATA2, 300*4882a593Smuzhiyun GPIO3D2_HOST_DOUT2, 301*4882a593Smuzhiyun GPIO3D2_MAC_RXD2, 302*4882a593Smuzhiyun GPIO3D2_SDIO1_DATA2, 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun GPIO3D1_SHIFT = 4, 305*4882a593Smuzhiyun GPIO3D1_MASK = 7, 306*4882a593Smuzhiyun GPIO3D1_GPIO = 0, 307*4882a593Smuzhiyun GPIO3DL1_FLASH1_DATA1, 308*4882a593Smuzhiyun GPIO3D1_HOST_DOUT1, 309*4882a593Smuzhiyun GPIO3D1_MAC_TXD3, 310*4882a593Smuzhiyun GPIO3D1_SDIO1_DATA1, 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun GPIO3D0_SHIFT = 0, 313*4882a593Smuzhiyun GPIO3D0_MASK = 7, 314*4882a593Smuzhiyun GPIO3D0_GPIO = 0, 315*4882a593Smuzhiyun GPIO3D0_FLASH1_DATA0, 316*4882a593Smuzhiyun GPIO3D0_HOST_DOUT0, 317*4882a593Smuzhiyun GPIO3D0_MAC_TXD2, 318*4882a593Smuzhiyun GPIO3D0_SDIO1_DATA0, 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* GRF_GPIO3HL_IOMUX */ 322*4882a593Smuzhiyun enum { 323*4882a593Smuzhiyun GPIO3D7_SHIFT = 12, 324*4882a593Smuzhiyun GPIO3D7_MASK = 7, 325*4882a593Smuzhiyun GPIO3D7_GPIO = 0, 326*4882a593Smuzhiyun GPIO3D7_FLASH1_DATA7, 327*4882a593Smuzhiyun GPIO3D7_HOST_DOUT7, 328*4882a593Smuzhiyun GPIO3D7_MAC_RXD1, 329*4882a593Smuzhiyun GPIO3D7_SDIO1_INTN, 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun GPIO3D6_SHIFT = 8, 332*4882a593Smuzhiyun GPIO3D6_MASK = 7, 333*4882a593Smuzhiyun GPIO3D6_GPIO = 0, 334*4882a593Smuzhiyun GPIO3D6_FLASH1_DATA6, 335*4882a593Smuzhiyun GPIO3D6_HOST_DOUT6, 336*4882a593Smuzhiyun GPIO3D6_MAC_RXD0, 337*4882a593Smuzhiyun GPIO3D6_SDIO1_BKPWR, 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun GPIO3D5_SHIFT = 4, 340*4882a593Smuzhiyun GPIO3D5_MASK = 7, 341*4882a593Smuzhiyun GPIO3D5_GPIO = 0, 342*4882a593Smuzhiyun GPIO3D5_FLASH1_DATA5, 343*4882a593Smuzhiyun GPIO3D5_HOST_DOUT5, 344*4882a593Smuzhiyun GPIO3D5_MAC_TXD1, 345*4882a593Smuzhiyun GPIO3D5_SDIO1_WRPRT, 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun GPIO3D4_SHIFT = 0, 348*4882a593Smuzhiyun GPIO3D4_MASK = 7, 349*4882a593Smuzhiyun GPIO3D4_GPIO = 0, 350*4882a593Smuzhiyun GPIO3D4_FLASH1_DATA4, 351*4882a593Smuzhiyun GPIO3D4_HOST_DOUT4, 352*4882a593Smuzhiyun GPIO3D4_MAC_TXD0, 353*4882a593Smuzhiyun GPIO3D4_SDIO1_DETECTN, 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* GRF_GPIO4AL_IOMUX */ 357*4882a593Smuzhiyun enum { 358*4882a593Smuzhiyun GPIO4A3_SHIFT = 12, 359*4882a593Smuzhiyun GPIO4A3_MASK = 7, 360*4882a593Smuzhiyun GPIO4A3_GPIO = 0, 361*4882a593Smuzhiyun GPIO4A3_FLASH1_ALE, 362*4882a593Smuzhiyun GPIO4A3_HOST_DOUT9, 363*4882a593Smuzhiyun GPIO4A3_MAC_CLK, 364*4882a593Smuzhiyun GPIO4A3_FLASH0_CSN6, 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun GPIO4A2_SHIFT = 8, 367*4882a593Smuzhiyun GPIO4A2_MASK = 7, 368*4882a593Smuzhiyun GPIO4A2_GPIO = 0, 369*4882a593Smuzhiyun GPIO4A2_FLASH1_RDN, 370*4882a593Smuzhiyun GPIO4A2_HOST_DOUT8, 371*4882a593Smuzhiyun GPIO4A2_MAC_RXER, 372*4882a593Smuzhiyun GPIO4A2_FLASH0_CSN5, 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun GPIO4A1_SHIFT = 4, 375*4882a593Smuzhiyun GPIO4A1_MASK = 7, 376*4882a593Smuzhiyun GPIO4A1_GPIO = 0, 377*4882a593Smuzhiyun GPIO4A1_FLASH1_WP, 378*4882a593Smuzhiyun GPIO4A1_HOST_CKOUTN, 379*4882a593Smuzhiyun GPIO4A1_MAC_TXDV, 380*4882a593Smuzhiyun GPIO4A1_FLASH0_CSN4, 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun GPIO4A0_SHIFT = 0, 383*4882a593Smuzhiyun GPIO4A0_MASK = 3, 384*4882a593Smuzhiyun GPIO4A0_GPIO = 0, 385*4882a593Smuzhiyun GPIO4A0_FLASH1_RDY, 386*4882a593Smuzhiyun GPIO4A0_HOST_CKOUTP, 387*4882a593Smuzhiyun GPIO4A0_MAC_MDC, 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* GRF_GPIO4AH_IOMUX */ 391*4882a593Smuzhiyun enum { 392*4882a593Smuzhiyun GPIO4A7_SHIFT = 12, 393*4882a593Smuzhiyun GPIO4A7_MASK = 7, 394*4882a593Smuzhiyun GPIO4A7_GPIO = 0, 395*4882a593Smuzhiyun GPIO4A7_FLASH1_CSN1, 396*4882a593Smuzhiyun GPIO4A7_HOST_DOUT13, 397*4882a593Smuzhiyun GPIO4A7_MAC_CSR, 398*4882a593Smuzhiyun GPIO4A7_SDIO1_CLKOUT, 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun GPIO4A6_SHIFT = 8, 401*4882a593Smuzhiyun GPIO4A6_MASK = 7, 402*4882a593Smuzhiyun GPIO4A6_GPIO = 0, 403*4882a593Smuzhiyun GPIO4A6_FLASH1_CSN0, 404*4882a593Smuzhiyun GPIO4A6_HOST_DOUT12, 405*4882a593Smuzhiyun GPIO4A6_MAC_RXCLK, 406*4882a593Smuzhiyun GPIO4A6_SDIO1_CMD, 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun GPIO4A5_SHIFT = 4, 409*4882a593Smuzhiyun GPIO4A5_MASK = 3, 410*4882a593Smuzhiyun GPIO4A5_GPIO = 0, 411*4882a593Smuzhiyun GPIO4A5_FLASH1_WRN, 412*4882a593Smuzhiyun GPIO4A5_HOST_DOUT11, 413*4882a593Smuzhiyun GPIO4A5_MAC_MDIO, 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun GPIO4A4_SHIFT = 0, 416*4882a593Smuzhiyun GPIO4A4_MASK = 7, 417*4882a593Smuzhiyun GPIO4A4_GPIO = 0, 418*4882a593Smuzhiyun GPIO4A4_FLASH1_CLE, 419*4882a593Smuzhiyun GPIO4A4_HOST_DOUT10, 420*4882a593Smuzhiyun GPIO4A4_MAC_TXEN, 421*4882a593Smuzhiyun GPIO4A4_FLASH0_CSN7, 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /* GRF_GPIO4BL_IOMUX */ 425*4882a593Smuzhiyun enum { 426*4882a593Smuzhiyun GPIO4B1_SHIFT = 4, 427*4882a593Smuzhiyun GPIO4B1_MASK = 7, 428*4882a593Smuzhiyun GPIO4B1_GPIO = 0, 429*4882a593Smuzhiyun GPIO4B1_FLASH1_CSN2, 430*4882a593Smuzhiyun GPIO4B1_HOST_DOUT15, 431*4882a593Smuzhiyun GPIO4B1_MAC_TXCLK, 432*4882a593Smuzhiyun GPIO4B1_SDIO1_PWREN, 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun GPIO4B0_SHIFT = 0, 435*4882a593Smuzhiyun GPIO4B0_MASK = 7, 436*4882a593Smuzhiyun GPIO4B0_GPIO = 0, 437*4882a593Smuzhiyun GPIO4B0_FLASH1_DQS, 438*4882a593Smuzhiyun GPIO4B0_HOST_DOUT14, 439*4882a593Smuzhiyun GPIO4B0_MAC_COL, 440*4882a593Smuzhiyun GPIO4B0_FLASH1_CSN3, 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun /* GRF_GPIO4C_IOMUX */ 444*4882a593Smuzhiyun enum { 445*4882a593Smuzhiyun GPIO4C7_SHIFT = 14, 446*4882a593Smuzhiyun GPIO4C7_MASK = 1, 447*4882a593Smuzhiyun GPIO4C7_GPIO = 0, 448*4882a593Smuzhiyun GPIO4C7_SDIO0_DATA3, 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun GPIO4C6_SHIFT = 12, 451*4882a593Smuzhiyun GPIO4C6_MASK = 1, 452*4882a593Smuzhiyun GPIO4C6_GPIO = 0, 453*4882a593Smuzhiyun GPIO4C6_SDIO0_DATA2, 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun GPIO4C5_SHIFT = 10, 456*4882a593Smuzhiyun GPIO4C5_MASK = 1, 457*4882a593Smuzhiyun GPIO4C5_GPIO = 0, 458*4882a593Smuzhiyun GPIO4C5_SDIO0_DATA1, 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun GPIO4C4_SHIFT = 8, 461*4882a593Smuzhiyun GPIO4C4_MASK = 1, 462*4882a593Smuzhiyun GPIO4C4_GPIO = 0, 463*4882a593Smuzhiyun GPIO4C4_SDIO0_DATA0, 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun GPIO4C3_SHIFT = 6, 466*4882a593Smuzhiyun GPIO4C3_MASK = 1, 467*4882a593Smuzhiyun GPIO4C3_GPIO = 0, 468*4882a593Smuzhiyun GPIO4C3_UART0BT_RTSN, 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun GPIO4C2_SHIFT = 4, 471*4882a593Smuzhiyun GPIO4C2_MASK = 1, 472*4882a593Smuzhiyun GPIO4C2_GPIO = 0, 473*4882a593Smuzhiyun GPIO4C2_UART0BT_CTSN, 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun GPIO4C1_SHIFT = 2, 476*4882a593Smuzhiyun GPIO4C1_MASK = 1, 477*4882a593Smuzhiyun GPIO4C1_GPIO = 0, 478*4882a593Smuzhiyun GPIO4C1_UART0BT_SOUT, 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun GPIO4C0_SHIFT = 0, 481*4882a593Smuzhiyun GPIO4C0_MASK = 1, 482*4882a593Smuzhiyun GPIO4C0_GPIO = 0, 483*4882a593Smuzhiyun GPIO4C0_UART0BT_SIN, 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun /* GRF_GPIO5B_IOMUX */ 487*4882a593Smuzhiyun enum { 488*4882a593Smuzhiyun GPIO5B7_SHIFT = 14, 489*4882a593Smuzhiyun GPIO5B7_MASK = 3, 490*4882a593Smuzhiyun GPIO5B7_GPIO = 0, 491*4882a593Smuzhiyun GPIO5B7_SPI0_RXD, 492*4882a593Smuzhiyun GPIO5B7_TS0_DATA7, 493*4882a593Smuzhiyun GPIO5B7_UART4EXP_SIN, 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun GPIO5B6_SHIFT = 12, 496*4882a593Smuzhiyun GPIO5B6_MASK = 3, 497*4882a593Smuzhiyun GPIO5B6_GPIO = 0, 498*4882a593Smuzhiyun GPIO5B6_SPI0_TXD, 499*4882a593Smuzhiyun GPIO5B6_TS0_DATA6, 500*4882a593Smuzhiyun GPIO5B6_UART4EXP_SOUT, 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun GPIO5B5_SHIFT = 10, 503*4882a593Smuzhiyun GPIO5B5_MASK = 3, 504*4882a593Smuzhiyun GPIO5B5_GPIO = 0, 505*4882a593Smuzhiyun GPIO5B5_SPI0_CSN0, 506*4882a593Smuzhiyun GPIO5B5_TS0_DATA5, 507*4882a593Smuzhiyun GPIO5B5_UART4EXP_RTSN, 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun GPIO5B4_SHIFT = 8, 510*4882a593Smuzhiyun GPIO5B4_MASK = 3, 511*4882a593Smuzhiyun GPIO5B4_GPIO = 0, 512*4882a593Smuzhiyun GPIO5B4_SPI0_CLK, 513*4882a593Smuzhiyun GPIO5B4_TS0_DATA4, 514*4882a593Smuzhiyun GPIO5B4_UART4EXP_CTSN, 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun GPIO5B3_SHIFT = 6, 517*4882a593Smuzhiyun GPIO5B3_MASK = 3, 518*4882a593Smuzhiyun GPIO5B3_GPIO = 0, 519*4882a593Smuzhiyun GPIO5B3_UART1BB_RTSN, 520*4882a593Smuzhiyun GPIO5B3_TS0_DATA3, 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun GPIO5B2_SHIFT = 4, 523*4882a593Smuzhiyun GPIO5B2_MASK = 3, 524*4882a593Smuzhiyun GPIO5B2_GPIO = 0, 525*4882a593Smuzhiyun GPIO5B2_UART1BB_CTSN, 526*4882a593Smuzhiyun GPIO5B2_TS0_DATA2, 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun GPIO5B1_SHIFT = 2, 529*4882a593Smuzhiyun GPIO5B1_MASK = 3, 530*4882a593Smuzhiyun GPIO5B1_GPIO = 0, 531*4882a593Smuzhiyun GPIO5B1_UART1BB_SOUT, 532*4882a593Smuzhiyun GPIO5B1_TS0_DATA1, 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun GPIO5B0_SHIFT = 0, 535*4882a593Smuzhiyun GPIO5B0_MASK = 3, 536*4882a593Smuzhiyun GPIO5B0_GPIO = 0, 537*4882a593Smuzhiyun GPIO5B0_UART1BB_SIN, 538*4882a593Smuzhiyun GPIO5B0_TS0_DATA0, 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun /* GRF_GPIO5C_IOMUX */ 542*4882a593Smuzhiyun enum { 543*4882a593Smuzhiyun GPIO5C3_SHIFT = 6, 544*4882a593Smuzhiyun GPIO5C3_MASK = 1, 545*4882a593Smuzhiyun GPIO5C3_GPIO = 0, 546*4882a593Smuzhiyun GPIO5C3_TS0_ERR, 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun GPIO5C2_SHIFT = 4, 549*4882a593Smuzhiyun GPIO5C2_MASK = 1, 550*4882a593Smuzhiyun GPIO5C2_GPIO = 0, 551*4882a593Smuzhiyun GPIO5C2_TS0_CLK, 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun GPIO5C1_SHIFT = 2, 554*4882a593Smuzhiyun GPIO5C1_MASK = 1, 555*4882a593Smuzhiyun GPIO5C1_GPIO = 0, 556*4882a593Smuzhiyun GPIO5C1_TS0_VALID, 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun GPIO5C0_SHIFT = 0, 559*4882a593Smuzhiyun GPIO5C0_MASK = 3, 560*4882a593Smuzhiyun GPIO5C0_GPIO = 0, 561*4882a593Smuzhiyun GPIO5C0_SPI0_CSN1, 562*4882a593Smuzhiyun GPIO5C0_TS0_SYNC, 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun /* GRF_GPIO6B_IOMUX */ 566*4882a593Smuzhiyun enum { 567*4882a593Smuzhiyun GPIO6B3_SHIFT = 6, 568*4882a593Smuzhiyun GPIO6B3_MASK = 1, 569*4882a593Smuzhiyun GPIO6B3_GPIO = 0, 570*4882a593Smuzhiyun GPIO6B3_SPDIF_TX, 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun GPIO6B2_SHIFT = 4, 573*4882a593Smuzhiyun GPIO6B2_MASK = 1, 574*4882a593Smuzhiyun GPIO6B2_GPIO = 0, 575*4882a593Smuzhiyun GPIO6B2_I2C1AUDIO_SCL, 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun GPIO6B1_SHIFT = 2, 578*4882a593Smuzhiyun GPIO6B1_MASK = 1, 579*4882a593Smuzhiyun GPIO6B1_GPIO = 0, 580*4882a593Smuzhiyun GPIO6B1_I2C1AUDIO_SDA, 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun GPIO6B0_SHIFT = 0, 583*4882a593Smuzhiyun GPIO6B0_MASK = 1, 584*4882a593Smuzhiyun GPIO6B0_GPIO = 0, 585*4882a593Smuzhiyun GPIO6B0_I2S_CLK, 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun /* GRF_GPIO6C_IOMUX */ 589*4882a593Smuzhiyun enum { 590*4882a593Smuzhiyun GPIO6C6_SHIFT = 12, 591*4882a593Smuzhiyun GPIO6C6_MASK = 1, 592*4882a593Smuzhiyun GPIO6C6_GPIO = 0, 593*4882a593Smuzhiyun GPIO6C6_SDMMC0_DECTN, 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun GPIO6C5_SHIFT = 10, 596*4882a593Smuzhiyun GPIO6C5_MASK = 1, 597*4882a593Smuzhiyun GPIO6C5_GPIO = 0, 598*4882a593Smuzhiyun GPIO6C5_SDMMC0_CMD, 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun GPIO6C4_SHIFT = 8, 601*4882a593Smuzhiyun GPIO6C4_MASK = 3, 602*4882a593Smuzhiyun GPIO6C4_GPIO = 0, 603*4882a593Smuzhiyun GPIO6C4_SDMMC0_CLKOUT, 604*4882a593Smuzhiyun GPIO6C4_JTAG_TDO, 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun GPIO6C3_SHIFT = 6, 607*4882a593Smuzhiyun GPIO6C3_MASK = 3, 608*4882a593Smuzhiyun GPIO6C3_GPIO = 0, 609*4882a593Smuzhiyun GPIO6C3_SDMMC0_DATA3, 610*4882a593Smuzhiyun GPIO6C3_JTAG_TCK, 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun GPIO6C2_SHIFT = 4, 613*4882a593Smuzhiyun GPIO6C2_MASK = 3, 614*4882a593Smuzhiyun GPIO6C2_GPIO = 0, 615*4882a593Smuzhiyun GPIO6C2_SDMMC0_DATA2, 616*4882a593Smuzhiyun GPIO6C2_JTAG_TDI, 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun GPIO6C1_SHIFT = 2, 619*4882a593Smuzhiyun GPIO6C1_MASK = 3, 620*4882a593Smuzhiyun GPIO6C1_GPIO = 0, 621*4882a593Smuzhiyun GPIO6C1_SDMMC0_DATA1, 622*4882a593Smuzhiyun GPIO6C1_JTAG_TRSTN, 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun GPIO6C0_SHIFT = 0, 625*4882a593Smuzhiyun GPIO6C0_MASK = 3, 626*4882a593Smuzhiyun GPIO6C0_GPIO = 0, 627*4882a593Smuzhiyun GPIO6C0_SDMMC0_DATA0, 628*4882a593Smuzhiyun GPIO6C0_JTAG_TMS, 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun /* GRF_GPIO7A_IOMUX */ 632*4882a593Smuzhiyun enum { 633*4882a593Smuzhiyun GPIO7A7_SHIFT = 14, 634*4882a593Smuzhiyun GPIO7A7_MASK = 3, 635*4882a593Smuzhiyun GPIO7A7_GPIO = 0, 636*4882a593Smuzhiyun GPIO7A7_UART3GPS_SIN, 637*4882a593Smuzhiyun GPIO7A7_GPS_MAG, 638*4882a593Smuzhiyun GPIO7A7_HSADCT1_DATA0, 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun GPIO7A1_SHIFT = 2, 641*4882a593Smuzhiyun GPIO7A1_MASK = 1, 642*4882a593Smuzhiyun GPIO7A1_GPIO = 0, 643*4882a593Smuzhiyun GPIO7A1_PWM_1, 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun GPIO7A0_SHIFT = 0, 646*4882a593Smuzhiyun GPIO7A0_MASK = 3, 647*4882a593Smuzhiyun GPIO7A0_GPIO = 0, 648*4882a593Smuzhiyun GPIO7A0_PWM_0, 649*4882a593Smuzhiyun GPIO7A0_VOP0_PWM, 650*4882a593Smuzhiyun GPIO7A0_VOP1_PWM, 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun /* GRF_GPIO7B_IOMUX */ 654*4882a593Smuzhiyun enum { 655*4882a593Smuzhiyun GPIO7B7_SHIFT = 14, 656*4882a593Smuzhiyun GPIO7B7_MASK = 3, 657*4882a593Smuzhiyun GPIO7B7_GPIO = 0, 658*4882a593Smuzhiyun GPIO7B7_ISP_SHUTTERTRIG, 659*4882a593Smuzhiyun GPIO7B7_SPI1_TXD, 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun GPIO7B6_SHIFT = 12, 662*4882a593Smuzhiyun GPIO7B6_MASK = 3, 663*4882a593Smuzhiyun GPIO7B6_GPIO = 0, 664*4882a593Smuzhiyun GPIO7B6_ISP_PRELIGHTTRIG, 665*4882a593Smuzhiyun GPIO7B6_SPI1_RXD, 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun GPIO7B5_SHIFT = 10, 668*4882a593Smuzhiyun GPIO7B5_MASK = 3, 669*4882a593Smuzhiyun GPIO7B5_GPIO = 0, 670*4882a593Smuzhiyun GPIO7B5_ISP_FLASHTRIGOUT, 671*4882a593Smuzhiyun GPIO7B5_SPI1_CSN0, 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun GPIO7B4_SHIFT = 8, 674*4882a593Smuzhiyun GPIO7B4_MASK = 3, 675*4882a593Smuzhiyun GPIO7B4_GPIO = 0, 676*4882a593Smuzhiyun GPIO7B4_ISP_SHUTTEREN, 677*4882a593Smuzhiyun GPIO7B4_SPI1_CLK, 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun GPIO7B3_SHIFT = 6, 680*4882a593Smuzhiyun GPIO7B3_MASK = 3, 681*4882a593Smuzhiyun GPIO7B3_GPIO = 0, 682*4882a593Smuzhiyun GPIO7B3_USB_DRVVBUS1, 683*4882a593Smuzhiyun GPIO7B3_EDP_HOTPLUG, 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun GPIO7B2_SHIFT = 4, 686*4882a593Smuzhiyun GPIO7B2_MASK = 3, 687*4882a593Smuzhiyun GPIO7B2_GPIO = 0, 688*4882a593Smuzhiyun GPIO7B2_UART3GPS_RTSN, 689*4882a593Smuzhiyun GPIO7B2_USB_DRVVBUS0, 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun GPIO7B1_SHIFT = 2, 692*4882a593Smuzhiyun GPIO7B1_MASK = 3, 693*4882a593Smuzhiyun GPIO7B1_GPIO = 0, 694*4882a593Smuzhiyun GPIO7B1_UART3GPS_CTSN, 695*4882a593Smuzhiyun GPIO7B1_GPS_RFCLK, 696*4882a593Smuzhiyun GPIO7B1_GPST1_CLK, 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun GPIO7B0_SHIFT = 0, 699*4882a593Smuzhiyun GPIO7B0_MASK = 3, 700*4882a593Smuzhiyun GPIO7B0_GPIO = 0, 701*4882a593Smuzhiyun GPIO7B0_UART3GPS_SOUT, 702*4882a593Smuzhiyun GPIO7B0_GPS_SIG, 703*4882a593Smuzhiyun GPIO7B0_HSADCT1_DATA1, 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun /* GRF_GPIO7CL_IOMUX */ 707*4882a593Smuzhiyun enum { 708*4882a593Smuzhiyun GPIO7C3_SHIFT = 12, 709*4882a593Smuzhiyun GPIO7C3_MASK = 3, 710*4882a593Smuzhiyun GPIO7C3_GPIO = 0, 711*4882a593Smuzhiyun GPIO7C3_I2C5HDMI_SDA, 712*4882a593Smuzhiyun GPIO7C3_EDPHDMII2C_SDA, 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun GPIO7C2_SHIFT = 8, 715*4882a593Smuzhiyun GPIO7C2_MASK = 1, 716*4882a593Smuzhiyun GPIO7C2_GPIO = 0, 717*4882a593Smuzhiyun GPIO7C2_I2C4TP_SCL, 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun GPIO7C1_SHIFT = 4, 720*4882a593Smuzhiyun GPIO7C1_MASK = 1, 721*4882a593Smuzhiyun GPIO7C1_GPIO = 0, 722*4882a593Smuzhiyun GPIO7C1_I2C4TP_SDA, 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun GPIO7C0_SHIFT = 0, 725*4882a593Smuzhiyun GPIO7C0_MASK = 3, 726*4882a593Smuzhiyun GPIO7C0_GPIO = 0, 727*4882a593Smuzhiyun GPIO7C0_ISP_FLASHTRIGIN, 728*4882a593Smuzhiyun GPIO7C0_EDPHDMI_CECINOUTT1, 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun /* GRF_GPIO7CH_IOMUX */ 732*4882a593Smuzhiyun enum { 733*4882a593Smuzhiyun GPIO7C7_SHIFT = 12, 734*4882a593Smuzhiyun GPIO7C7_MASK = 7, 735*4882a593Smuzhiyun GPIO7C7_GPIO = 0, 736*4882a593Smuzhiyun GPIO7C7_UART2DBG_SOUT, 737*4882a593Smuzhiyun GPIO7C7_UART2DBG_SIROUT, 738*4882a593Smuzhiyun GPIO7C7_PWM_3, 739*4882a593Smuzhiyun GPIO7C7_EDPHDMI_CECINOUT, 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun GPIO7C6_SHIFT = 8, 742*4882a593Smuzhiyun GPIO7C6_MASK = 3, 743*4882a593Smuzhiyun GPIO7C6_GPIO = 0, 744*4882a593Smuzhiyun GPIO7C6_UART2DBG_SIN, 745*4882a593Smuzhiyun GPIO7C6_UART2DBG_SIRIN, 746*4882a593Smuzhiyun GPIO7C6_PWM_2, 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun GPIO7C4_SHIFT = 0, 749*4882a593Smuzhiyun GPIO7C4_MASK = 3, 750*4882a593Smuzhiyun GPIO7C4_GPIO = 0, 751*4882a593Smuzhiyun GPIO7C4_I2C5HDMI_SCL, 752*4882a593Smuzhiyun GPIO7C4_EDPHDMII2C_SCL, 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun /* GRF_GPIO8A_IOMUX */ 756*4882a593Smuzhiyun enum { 757*4882a593Smuzhiyun GPIO8A7_SHIFT = 14, 758*4882a593Smuzhiyun GPIO8A7_MASK = 3, 759*4882a593Smuzhiyun GPIO8A7_GPIO = 0, 760*4882a593Smuzhiyun GPIO8A7_SPI2_CSN0, 761*4882a593Smuzhiyun GPIO8A7_SC_DETECT, 762*4882a593Smuzhiyun GPIO8A7_RESERVE, 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun GPIO8A6_SHIFT = 12, 765*4882a593Smuzhiyun GPIO8A6_MASK = 3, 766*4882a593Smuzhiyun GPIO8A6_GPIO = 0, 767*4882a593Smuzhiyun GPIO8A6_SPI2_CLK, 768*4882a593Smuzhiyun GPIO8A6_SC_IO, 769*4882a593Smuzhiyun GPIO8A6_RESERVE, 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun GPIO8A5_SHIFT = 10, 772*4882a593Smuzhiyun GPIO8A5_MASK = 3, 773*4882a593Smuzhiyun GPIO8A5_GPIO = 0, 774*4882a593Smuzhiyun GPIO8A5_I2C2SENSOR_SCL, 775*4882a593Smuzhiyun GPIO8A5_SC_CLK, 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun GPIO8A4_SHIFT = 8, 778*4882a593Smuzhiyun GPIO8A4_MASK = 3, 779*4882a593Smuzhiyun GPIO8A4_GPIO = 0, 780*4882a593Smuzhiyun GPIO8A4_I2C2SENSOR_SDA, 781*4882a593Smuzhiyun GPIO8A4_SC_RST, 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun GPIO8A3_SHIFT = 6, 784*4882a593Smuzhiyun GPIO8A3_MASK = 3, 785*4882a593Smuzhiyun GPIO8A3_GPIO = 0, 786*4882a593Smuzhiyun GPIO8A3_SPI2_CSN1, 787*4882a593Smuzhiyun GPIO8A3_SC_IOT1, 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun GPIO8A2_SHIFT = 4, 790*4882a593Smuzhiyun GPIO8A2_MASK = 1, 791*4882a593Smuzhiyun GPIO8A2_GPIO = 0, 792*4882a593Smuzhiyun GPIO8A2_SC_DETECTT1, 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun GPIO8A1_SHIFT = 2, 795*4882a593Smuzhiyun GPIO8A1_MASK = 3, 796*4882a593Smuzhiyun GPIO8A1_GPIO = 0, 797*4882a593Smuzhiyun GPIO8A1_PS2_DATA, 798*4882a593Smuzhiyun GPIO8A1_SC_VCC33V, 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun GPIO8A0_SHIFT = 0, 801*4882a593Smuzhiyun GPIO8A0_MASK = 3, 802*4882a593Smuzhiyun GPIO8A0_GPIO = 0, 803*4882a593Smuzhiyun GPIO8A0_PS2_CLK, 804*4882a593Smuzhiyun GPIO8A0_SC_VCC18V, 805*4882a593Smuzhiyun }; 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun /* GRF_GPIO8B_IOMUX */ 808*4882a593Smuzhiyun enum { 809*4882a593Smuzhiyun GPIO8B1_SHIFT = 2, 810*4882a593Smuzhiyun GPIO8B1_MASK = 3, 811*4882a593Smuzhiyun GPIO8B1_GPIO = 0, 812*4882a593Smuzhiyun GPIO8B1_SPI2_TXD, 813*4882a593Smuzhiyun GPIO8B1_SC_CLK, 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun GPIO8B0_SHIFT = 0, 816*4882a593Smuzhiyun GPIO8B0_MASK = 3, 817*4882a593Smuzhiyun GPIO8B0_GPIO = 0, 818*4882a593Smuzhiyun GPIO8B0_SPI2_RXD, 819*4882a593Smuzhiyun GPIO8B0_SC_RST, 820*4882a593Smuzhiyun }; 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun /* GRF_SOC_CON0 */ 823*4882a593Smuzhiyun enum { 824*4882a593Smuzhiyun PAUSE_MMC_PERI_SHIFT = 0xf, 825*4882a593Smuzhiyun PAUSE_MMC_PERI_MASK = 1, 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun PAUSE_EMEM_PERI_SHIFT = 0xe, 828*4882a593Smuzhiyun PAUSE_EMEM_PERI_MASK = 1, 829*4882a593Smuzhiyun 830*4882a593Smuzhiyun PAUSE_USB_PERI_SHIFT = 0xd, 831*4882a593Smuzhiyun PAUSE_USB_PERI_MASK = 1, 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun GRF_FORCE_JTAG_SHIFT = 0xc, 834*4882a593Smuzhiyun GRF_FORCE_JTAG_MASK = 1, 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb, 837*4882a593Smuzhiyun GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1, 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa, 840*4882a593Smuzhiyun GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1, 841*4882a593Smuzhiyun 842*4882a593Smuzhiyun DDR1_16BIT_EN_SHIFT = 9, 843*4882a593Smuzhiyun DDR1_16BIT_EN_MASK = 1, 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun DDR0_16BIT_EN_SHIFT = 8, 846*4882a593Smuzhiyun DDR0_16BIT_EN_MASK = 1, 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun VCODEC_SHIFT = 7, 849*4882a593Smuzhiyun VCODEC_MASK = 1, 850*4882a593Smuzhiyun VCODEC_SELECT_VEPU_ACLK = 0, 851*4882a593Smuzhiyun VCODEC_SELECT_VDPU_ACLK, 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun UPCTL1_C_ACTIVE_IN_SHIFT = 6, 854*4882a593Smuzhiyun UPCTL1_C_ACTIVE_IN_MASK = 1, 855*4882a593Smuzhiyun UPCTL1_C_ACTIVE_IN_MAY = 0, 856*4882a593Smuzhiyun UPCTL1_C_ACTIVE_IN_WILL, 857*4882a593Smuzhiyun 858*4882a593Smuzhiyun UPCTL0_C_ACTIVE_IN_SHIFT = 5, 859*4882a593Smuzhiyun UPCTL0_C_ACTIVE_IN_MASK = 1, 860*4882a593Smuzhiyun UPCTL0_C_ACTIVE_IN_MAY = 0, 861*4882a593Smuzhiyun UPCTL0_C_ACTIVE_IN_WILL, 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun MSCH1_MAINDDR3_SHIFT = 4, 864*4882a593Smuzhiyun MSCH1_MAINDDR3_MASK = 1, 865*4882a593Smuzhiyun MSCH1_MAINDDR3_DDR3 = 1, 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun MSCH0_MAINDDR3_SHIFT = 3, 868*4882a593Smuzhiyun MSCH0_MAINDDR3_MASK = 1, 869*4882a593Smuzhiyun MSCH0_MAINDDR3_DDR3 = 1, 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun MSCH1_MAINPARTIALPOP_SHIFT = 2, 872*4882a593Smuzhiyun MSCH1_MAINPARTIALPOP_MASK = 1, 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun MSCH0_MAINPARTIALPOP_SHIFT = 1, 875*4882a593Smuzhiyun MSCH0_MAINPARTIALPOP_MASK = 1, 876*4882a593Smuzhiyun }; 877*4882a593Smuzhiyun 878*4882a593Smuzhiyun /* GRF_SOC_CON1 */ 879*4882a593Smuzhiyun enum { 880*4882a593Smuzhiyun RK3288_RMII_MODE_SHIFT = 14, 881*4882a593Smuzhiyun RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), 882*4882a593Smuzhiyun RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT), 883*4882a593Smuzhiyun 884*4882a593Smuzhiyun RK3288_GMAC_CLK_SEL_SHIFT = 12, 885*4882a593Smuzhiyun RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), 886*4882a593Smuzhiyun RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), 887*4882a593Smuzhiyun RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), 888*4882a593Smuzhiyun RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT), 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun RK3288_RMII_CLK_SEL_SHIFT = 11, 891*4882a593Smuzhiyun RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), 892*4882a593Smuzhiyun RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), 893*4882a593Smuzhiyun RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun GMAC_SPEED_SHIFT = 0xa, 896*4882a593Smuzhiyun GMAC_SPEED_MASK = 1, 897*4882a593Smuzhiyun GMAC_SPEED_10M = 0, 898*4882a593Smuzhiyun GMAC_SPEED_100M, 899*4882a593Smuzhiyun 900*4882a593Smuzhiyun GMAC_FLOWCTRL_SHIFT = 0x9, 901*4882a593Smuzhiyun GMAC_FLOWCTRL_MASK = 1, 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, 904*4882a593Smuzhiyun RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 905*4882a593Smuzhiyun RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 906*4882a593Smuzhiyun RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun HOST_REMAP_SHIFT = 0x5, 909*4882a593Smuzhiyun HOST_REMAP_MASK = 1 910*4882a593Smuzhiyun }; 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun /* GRF_SOC_CON2 */ 913*4882a593Smuzhiyun enum { 914*4882a593Smuzhiyun UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, 915*4882a593Smuzhiyun UPCTL1_LPDDR3_ODT_EN_MASK = 1, 916*4882a593Smuzhiyun UPCTL1_LPDDR3_ODT_EN_ODT = 1, 917*4882a593Smuzhiyun 918*4882a593Smuzhiyun UPCTL1_BST_DIABLE_SHIFT = 0xc, 919*4882a593Smuzhiyun UPCTL1_BST_DIABLE_MASK = 1, 920*4882a593Smuzhiyun UPCTL1_BST_DIABLE_DISABLE = 1, 921*4882a593Smuzhiyun 922*4882a593Smuzhiyun LPDDR3_EN1_SHIFT = 0xb, 923*4882a593Smuzhiyun LPDDR3_EN1_MASK = 1, 924*4882a593Smuzhiyun LPDDR3_EN1_LPDDR3 = 1, 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa, 927*4882a593Smuzhiyun UPCTL0_LPDDR3_ODT_EN_MASK = 1, 928*4882a593Smuzhiyun UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1, 929*4882a593Smuzhiyun 930*4882a593Smuzhiyun UPCTL0_BST_DIABLE_SHIFT = 9, 931*4882a593Smuzhiyun UPCTL0_BST_DIABLE_MASK = 1, 932*4882a593Smuzhiyun UPCTL0_BST_DIABLE_DISABLE = 1, 933*4882a593Smuzhiyun 934*4882a593Smuzhiyun LPDDR3_EN0_SHIFT = 8, 935*4882a593Smuzhiyun LPDDR3_EN0_MASK = 1, 936*4882a593Smuzhiyun LPDDR3_EN0_LPDDR3 = 1, 937*4882a593Smuzhiyun 938*4882a593Smuzhiyun GRF_POC_FLASH0_CTRL_SHIFT = 7, 939*4882a593Smuzhiyun GRF_POC_FLASH0_CTRL_MASK = 1, 940*4882a593Smuzhiyun GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0, 941*4882a593Smuzhiyun GRF_POC_FLASH0_CTRL_GRF_IO_VSEL, 942*4882a593Smuzhiyun 943*4882a593Smuzhiyun SIMCARD_MUX_SHIFT = 6, 944*4882a593Smuzhiyun SIMCARD_MUX_MASK = 1, 945*4882a593Smuzhiyun SIMCARD_MUX_USE_A = 1, 946*4882a593Smuzhiyun SIMCARD_MUX_USE_B = 0, 947*4882a593Smuzhiyun 948*4882a593Smuzhiyun GRF_SPDIF_2CH_EN_SHIFT = 1, 949*4882a593Smuzhiyun GRF_SPDIF_2CH_EN_MASK = 1, 950*4882a593Smuzhiyun GRF_SPDIF_2CH_EN_8CH = 0, 951*4882a593Smuzhiyun GRF_SPDIF_2CH_EN_2CH, 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun PWM_SHIFT = 0, 954*4882a593Smuzhiyun PWM_MASK = 1, 955*4882a593Smuzhiyun PWM_RK = 1, 956*4882a593Smuzhiyun PWM_PWM = 0, 957*4882a593Smuzhiyun }; 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun /* GRF_SOC_CON3 */ 960*4882a593Smuzhiyun enum { 961*4882a593Smuzhiyun RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, 962*4882a593Smuzhiyun RK3288_RXCLK_DLY_ENA_GMAC_MASK = 963*4882a593Smuzhiyun (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), 964*4882a593Smuzhiyun RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 965*4882a593Smuzhiyun RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = 966*4882a593Smuzhiyun (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, 969*4882a593Smuzhiyun RK3288_TXCLK_DLY_ENA_GMAC_MASK = 970*4882a593Smuzhiyun (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), 971*4882a593Smuzhiyun RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 972*4882a593Smuzhiyun RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = 973*4882a593Smuzhiyun (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), 974*4882a593Smuzhiyun 975*4882a593Smuzhiyun RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 976*4882a593Smuzhiyun RK3288_CLK_RX_DL_CFG_GMAC_MASK = 977*4882a593Smuzhiyun (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), 978*4882a593Smuzhiyun 979*4882a593Smuzhiyun RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 980*4882a593Smuzhiyun RK3288_CLK_TX_DL_CFG_GMAC_MASK = 981*4882a593Smuzhiyun (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), 982*4882a593Smuzhiyun }; 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun /* GRF_SOC_CON6 */ 985*4882a593Smuzhiyun enum GRF_SOC_CON6 { 986*4882a593Smuzhiyun RK3288_HDMI_EDP_SEL_SHIFT = 0xf, 987*4882a593Smuzhiyun RK3288_HDMI_EDP_SEL_MASK = 988*4882a593Smuzhiyun 1 << RK3288_HDMI_EDP_SEL_SHIFT, 989*4882a593Smuzhiyun RK3288_HDMI_EDP_SEL_EDP = 0, 990*4882a593Smuzhiyun RK3288_HDMI_EDP_SEL_HDMI, 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun RK3288_DSI0_DPICOLORM_SHIFT = 0x8, 993*4882a593Smuzhiyun RK3288_DSI0_DPICOLORM_MASK = 994*4882a593Smuzhiyun 1 << RK3288_DSI0_DPICOLORM_SHIFT, 995*4882a593Smuzhiyun 996*4882a593Smuzhiyun RK3288_DSI0_DPISHUTDN_SHIFT = 0x7, 997*4882a593Smuzhiyun RK3288_DSI0_DPISHUTDN_MASK = 998*4882a593Smuzhiyun 1 << RK3288_DSI0_DPISHUTDN_SHIFT, 999*4882a593Smuzhiyun 1000*4882a593Smuzhiyun RK3288_DSI0_LCDC_SEL_SHIFT = 0x6, 1001*4882a593Smuzhiyun RK3288_DSI0_LCDC_SEL_MASK = 1002*4882a593Smuzhiyun 1 << RK3288_DSI0_LCDC_SEL_SHIFT, 1003*4882a593Smuzhiyun RK3288_DSI0_LCDC_SEL_BIG = 0, 1004*4882a593Smuzhiyun RK3288_DSI0_LCDC_SEL_LIT = 1, 1005*4882a593Smuzhiyun 1006*4882a593Smuzhiyun RK3288_EDP_LCDC_SEL_SHIFT = 0x5, 1007*4882a593Smuzhiyun RK3288_EDP_LCDC_SEL_MASK = 1008*4882a593Smuzhiyun 1 << RK3288_EDP_LCDC_SEL_SHIFT, 1009*4882a593Smuzhiyun RK3288_EDP_LCDC_SEL_BIG = 0, 1010*4882a593Smuzhiyun RK3288_EDP_LCDC_SEL_LIT = 1, 1011*4882a593Smuzhiyun 1012*4882a593Smuzhiyun RK3288_HDMI_LCDC_SEL_SHIFT = 0x4, 1013*4882a593Smuzhiyun RK3288_HDMI_LCDC_SEL_MASK = 1014*4882a593Smuzhiyun 1 << RK3288_HDMI_LCDC_SEL_SHIFT, 1015*4882a593Smuzhiyun RK3288_HDMI_LCDC_SEL_BIG = 0, 1016*4882a593Smuzhiyun RK3288_HDMI_LCDC_SEL_LIT = 1, 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun RK3288_LVDS_LCDC_SEL_SHIFT = 0x3, 1019*4882a593Smuzhiyun RK3288_LVDS_LCDC_SEL_MASK = 1020*4882a593Smuzhiyun 1 << RK3288_LVDS_LCDC_SEL_SHIFT, 1021*4882a593Smuzhiyun RK3288_LVDS_LCDC_SEL_BIG = 0, 1022*4882a593Smuzhiyun RK3288_LVDS_LCDC_SEL_LIT = 1, 1023*4882a593Smuzhiyun }; 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun /* RK3288_SOC_CON8 */ 1026*4882a593Smuzhiyun enum GRF_SOC_CON8 { 1027*4882a593Smuzhiyun RK3288_DPHY_TX0_RXMODE_SHIFT = 4, 1028*4882a593Smuzhiyun RK3288_DPHY_TX0_RXMODE_MASK = 1029*4882a593Smuzhiyun 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT, 1030*4882a593Smuzhiyun RK3288_DPHY_TX0_RXMODE_EN = 0xf, 1031*4882a593Smuzhiyun RK3288_DPHY_TX0_RXMODE_DIS = 0, 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8, 1034*4882a593Smuzhiyun RK3288_DPHY_TX0_TXSTOPMODE_MASK = 1035*4882a593Smuzhiyun 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT, 1036*4882a593Smuzhiyun RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf, 1037*4882a593Smuzhiyun RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0, 1038*4882a593Smuzhiyun 1039*4882a593Smuzhiyun RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0, 1040*4882a593Smuzhiyun RK3288_DPHY_TX0_TURNREQUEST_MASK = 1041*4882a593Smuzhiyun 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT, 1042*4882a593Smuzhiyun RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf, 1043*4882a593Smuzhiyun RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, 1044*4882a593Smuzhiyun }; 1045*4882a593Smuzhiyun 1046*4882a593Smuzhiyun /* GPIO Bias settings */ 1047*4882a593Smuzhiyun enum GPIO_BIAS { 1048*4882a593Smuzhiyun GPIO_BIAS_2MA = 0, 1049*4882a593Smuzhiyun GPIO_BIAS_4MA, 1050*4882a593Smuzhiyun GPIO_BIAS_8MA, 1051*4882a593Smuzhiyun GPIO_BIAS_12MA, 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun #define GPIO_BIAS_MASK 0x3 1055*4882a593Smuzhiyun #define GPIO_BIAS_SHIFT(x) ((x) * 2) 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun enum GPIO_PU_PD { 1058*4882a593Smuzhiyun GPIO_PULL_NORMAL = 0, 1059*4882a593Smuzhiyun GPIO_PULL_UP, 1060*4882a593Smuzhiyun GPIO_PULL_DOWN, 1061*4882a593Smuzhiyun GPIO_PULL_REPEAT, 1062*4882a593Smuzhiyun }; 1063*4882a593Smuzhiyun 1064*4882a593Smuzhiyun #define GPIO_PULL_MASK 0x3 1065*4882a593Smuzhiyun #define GPIO_PULL_SHIFT(x) ((x) * 2) 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun #endif 1068