1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * PXA25x UDC definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __REGS_USB_H__ 10*4882a593Smuzhiyun #define __REGS_USB_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct pxa25x_udc_regs { 13*4882a593Smuzhiyun /* UDC Control Register */ 14*4882a593Smuzhiyun uint32_t udccr; /* 0x000 */ 15*4882a593Smuzhiyun uint32_t reserved1; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* UDC Control Function Register */ 18*4882a593Smuzhiyun uint32_t udccfr; /* 0x008 */ 19*4882a593Smuzhiyun uint32_t reserved2; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* UDC Endpoint Control/Status Registers */ 22*4882a593Smuzhiyun uint32_t udccs[16]; /* 0x010 - 0x04c */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* UDC Interrupt Control/Status Registers */ 25*4882a593Smuzhiyun uint32_t uicr0; /* 0x050 */ 26*4882a593Smuzhiyun uint32_t uicr1; /* 0x054 */ 27*4882a593Smuzhiyun uint32_t usir0; /* 0x058 */ 28*4882a593Smuzhiyun uint32_t usir1; /* 0x05c */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* UDC Frame Number/Byte Count Registers */ 31*4882a593Smuzhiyun uint32_t ufnrh; /* 0x060 */ 32*4882a593Smuzhiyun uint32_t ufnrl; /* 0x064 */ 33*4882a593Smuzhiyun uint32_t ubcr2; /* 0x068 */ 34*4882a593Smuzhiyun uint32_t ubcr4; /* 0x06c */ 35*4882a593Smuzhiyun uint32_t ubcr7; /* 0x070 */ 36*4882a593Smuzhiyun uint32_t ubcr9; /* 0x074 */ 37*4882a593Smuzhiyun uint32_t ubcr12; /* 0x078 */ 38*4882a593Smuzhiyun uint32_t ubcr14; /* 0x07c */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* UDC Endpoint Data Registers */ 41*4882a593Smuzhiyun uint32_t uddr0; /* 0x080 */ 42*4882a593Smuzhiyun uint32_t reserved3[7]; 43*4882a593Smuzhiyun uint32_t uddr5; /* 0x0a0 */ 44*4882a593Smuzhiyun uint32_t reserved4[7]; 45*4882a593Smuzhiyun uint32_t uddr10; /* 0x0c0 */ 46*4882a593Smuzhiyun uint32_t reserved5[7]; 47*4882a593Smuzhiyun uint32_t uddr15; /* 0x0e0 */ 48*4882a593Smuzhiyun uint32_t reserved6[7]; 49*4882a593Smuzhiyun uint32_t uddr1; /* 0x100 */ 50*4882a593Smuzhiyun uint32_t reserved7[31]; 51*4882a593Smuzhiyun uint32_t uddr2; /* 0x180 */ 52*4882a593Smuzhiyun uint32_t reserved8[31]; 53*4882a593Smuzhiyun uint32_t uddr3; /* 0x200 */ 54*4882a593Smuzhiyun uint32_t reserved9[127]; 55*4882a593Smuzhiyun uint32_t uddr4; /* 0x400 */ 56*4882a593Smuzhiyun uint32_t reserved10[127]; 57*4882a593Smuzhiyun uint32_t uddr6; /* 0x600 */ 58*4882a593Smuzhiyun uint32_t reserved11[31]; 59*4882a593Smuzhiyun uint32_t uddr7; /* 0x680 */ 60*4882a593Smuzhiyun uint32_t reserved12[31]; 61*4882a593Smuzhiyun uint32_t uddr8; /* 0x700 */ 62*4882a593Smuzhiyun uint32_t reserved13[127]; 63*4882a593Smuzhiyun uint32_t uddr9; /* 0x900 */ 64*4882a593Smuzhiyun uint32_t reserved14[127]; 65*4882a593Smuzhiyun uint32_t uddr11; /* 0xb00 */ 66*4882a593Smuzhiyun uint32_t reserved15[31]; 67*4882a593Smuzhiyun uint32_t uddr12; /* 0xb80 */ 68*4882a593Smuzhiyun uint32_t reserved16[31]; 69*4882a593Smuzhiyun uint32_t uddr13; /* 0xc00 */ 70*4882a593Smuzhiyun uint32_t reserved17[127]; 71*4882a593Smuzhiyun uint32_t uddr14; /* 0xe00 */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define PXA25X_UDC_BASE 0x40600000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define UDCCR_UDE (1 << 0) 78*4882a593Smuzhiyun #define UDCCR_UDA (1 << 1) 79*4882a593Smuzhiyun #define UDCCR_RSM (1 << 2) 80*4882a593Smuzhiyun #define UDCCR_RESIR (1 << 3) 81*4882a593Smuzhiyun #define UDCCR_SUSIR (1 << 4) 82*4882a593Smuzhiyun #define UDCCR_SRM (1 << 5) 83*4882a593Smuzhiyun #define UDCCR_RSTIR (1 << 6) 84*4882a593Smuzhiyun #define UDCCR_REM (1 << 7) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Bulk IN endpoint 1/6/11 */ 87*4882a593Smuzhiyun #define UDCCS_BI_TSP (1 << 7) 88*4882a593Smuzhiyun #define UDCCS_BI_FST (1 << 5) 89*4882a593Smuzhiyun #define UDCCS_BI_SST (1 << 4) 90*4882a593Smuzhiyun #define UDCCS_BI_TUR (1 << 3) 91*4882a593Smuzhiyun #define UDCCS_BI_FTF (1 << 2) 92*4882a593Smuzhiyun #define UDCCS_BI_TPC (1 << 1) 93*4882a593Smuzhiyun #define UDCCS_BI_TFS (1 << 0) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Bulk OUT endpoint 2/7/12 */ 96*4882a593Smuzhiyun #define UDCCS_BO_RSP (1 << 7) 97*4882a593Smuzhiyun #define UDCCS_BO_RNE (1 << 6) 98*4882a593Smuzhiyun #define UDCCS_BO_FST (1 << 5) 99*4882a593Smuzhiyun #define UDCCS_BO_SST (1 << 4) 100*4882a593Smuzhiyun #define UDCCS_BO_DME (1 << 3) 101*4882a593Smuzhiyun #define UDCCS_BO_RPC (1 << 1) 102*4882a593Smuzhiyun #define UDCCS_BO_RFS (1 << 0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Isochronous OUT endpoint 4/9/14 */ 105*4882a593Smuzhiyun #define UDCCS_IO_RSP (1 << 7) 106*4882a593Smuzhiyun #define UDCCS_IO_RNE (1 << 6) 107*4882a593Smuzhiyun #define UDCCS_IO_DME (1 << 3) 108*4882a593Smuzhiyun #define UDCCS_IO_ROF (1 << 2) 109*4882a593Smuzhiyun #define UDCCS_IO_RPC (1 << 1) 110*4882a593Smuzhiyun #define UDCCS_IO_RFS (1 << 0) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Control endpoint 0 */ 113*4882a593Smuzhiyun #define UDCCS0_OPR (1 << 0) 114*4882a593Smuzhiyun #define UDCCS0_IPR (1 << 1) 115*4882a593Smuzhiyun #define UDCCS0_FTF (1 << 2) 116*4882a593Smuzhiyun #define UDCCS0_DRWF (1 << 3) 117*4882a593Smuzhiyun #define UDCCS0_SST (1 << 4) 118*4882a593Smuzhiyun #define UDCCS0_FST (1 << 5) 119*4882a593Smuzhiyun #define UDCCS0_RNE (1 << 6) 120*4882a593Smuzhiyun #define UDCCS0_SA (1 << 7) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define UICR0_IM0 (1 << 0) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define USIR0_IR0 (1 << 0) 125*4882a593Smuzhiyun #define USIR0_IR1 (1 << 1) 126*4882a593Smuzhiyun #define USIR0_IR2 (1 << 2) 127*4882a593Smuzhiyun #define USIR0_IR3 (1 << 3) 128*4882a593Smuzhiyun #define USIR0_IR4 (1 << 4) 129*4882a593Smuzhiyun #define USIR0_IR5 (1 << 5) 130*4882a593Smuzhiyun #define USIR0_IR6 (1 << 6) 131*4882a593Smuzhiyun #define USIR0_IR7 (1 << 7) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ 134*4882a593Smuzhiyun #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ 135*4882a593Smuzhiyun /* 136*4882a593Smuzhiyun * Intel(R) PXA255 Processor Specification, September 2003 (page 31) 137*4882a593Smuzhiyun * define new "must be one" bits in UDCCFR (see Table 12-13.) 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ 142*4882a593Smuzhiyun #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ 143*4882a593Smuzhiyun #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ 144*4882a593Smuzhiyun #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ 145*4882a593Smuzhiyun #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* __REGS_USB_H__ */ 148