1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __REGS_UART_H__ 8*4882a593Smuzhiyun #define __REGS_UART_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define FFUART_BASE 0x40100000 11*4882a593Smuzhiyun #define BTUART_BASE 0x40200000 12*4882a593Smuzhiyun #define STUART_BASE 0x40700000 13*4882a593Smuzhiyun #define HWUART_BASE 0x41600000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct pxa_uart_regs { 16*4882a593Smuzhiyun union { 17*4882a593Smuzhiyun uint32_t thr; 18*4882a593Smuzhiyun uint32_t rbr; 19*4882a593Smuzhiyun uint32_t dll; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun union { 22*4882a593Smuzhiyun uint32_t ier; 23*4882a593Smuzhiyun uint32_t dlh; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun union { 26*4882a593Smuzhiyun uint32_t fcr; 27*4882a593Smuzhiyun uint32_t iir; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun uint32_t lcr; 30*4882a593Smuzhiyun uint32_t mcr; 31*4882a593Smuzhiyun uint32_t lsr; 32*4882a593Smuzhiyun uint32_t msr; 33*4882a593Smuzhiyun uint32_t spr; 34*4882a593Smuzhiyun uint32_t isr; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IER_DMAE (1 << 7) 38*4882a593Smuzhiyun #define IER_UUE (1 << 6) 39*4882a593Smuzhiyun #define IER_NRZE (1 << 5) 40*4882a593Smuzhiyun #define IER_RTIOE (1 << 4) 41*4882a593Smuzhiyun #define IER_MIE (1 << 3) 42*4882a593Smuzhiyun #define IER_RLSE (1 << 2) 43*4882a593Smuzhiyun #define IER_TIE (1 << 1) 44*4882a593Smuzhiyun #define IER_RAVIE (1 << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define IIR_FIFOES1 (1 << 7) 47*4882a593Smuzhiyun #define IIR_FIFOES0 (1 << 6) 48*4882a593Smuzhiyun #define IIR_TOD (1 << 3) 49*4882a593Smuzhiyun #define IIR_IID2 (1 << 2) 50*4882a593Smuzhiyun #define IIR_IID1 (1 << 1) 51*4882a593Smuzhiyun #define IIR_IP (1 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define FCR_ITL2 (1 << 7) 54*4882a593Smuzhiyun #define FCR_ITL1 (1 << 6) 55*4882a593Smuzhiyun #define FCR_RESETTF (1 << 2) 56*4882a593Smuzhiyun #define FCR_RESETRF (1 << 1) 57*4882a593Smuzhiyun #define FCR_TRFIFOE (1 << 0) 58*4882a593Smuzhiyun #define FCR_ITL_1 0 59*4882a593Smuzhiyun #define FCR_ITL_8 (FCR_ITL1) 60*4882a593Smuzhiyun #define FCR_ITL_16 (FCR_ITL2) 61*4882a593Smuzhiyun #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define LCR_DLAB (1 << 7) 64*4882a593Smuzhiyun #define LCR_SB (1 << 6) 65*4882a593Smuzhiyun #define LCR_STKYP (1 << 5) 66*4882a593Smuzhiyun #define LCR_EPS (1 << 4) 67*4882a593Smuzhiyun #define LCR_PEN (1 << 3) 68*4882a593Smuzhiyun #define LCR_STB (1 << 2) 69*4882a593Smuzhiyun #define LCR_WLS1 (1 << 1) 70*4882a593Smuzhiyun #define LCR_WLS0 (1 << 0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define LSR_FIFOE (1 << 7) 73*4882a593Smuzhiyun #define LSR_TEMT (1 << 6) 74*4882a593Smuzhiyun #define LSR_TDRQ (1 << 5) 75*4882a593Smuzhiyun #define LSR_BI (1 << 4) 76*4882a593Smuzhiyun #define LSR_FE (1 << 3) 77*4882a593Smuzhiyun #define LSR_PE (1 << 2) 78*4882a593Smuzhiyun #define LSR_OE (1 << 1) 79*4882a593Smuzhiyun #define LSR_DR (1 << 0) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define MCR_LOOP (1 << 4) 82*4882a593Smuzhiyun #define MCR_OUT2 (1 << 3) 83*4882a593Smuzhiyun #define MCR_OUT1 (1 << 2) 84*4882a593Smuzhiyun #define MCR_RTS (1 << 1) 85*4882a593Smuzhiyun #define MCR_DTR (1 << 0) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MSR_DCD (1 << 7) 88*4882a593Smuzhiyun #define MSR_RI (1 << 6) 89*4882a593Smuzhiyun #define MSR_DSR (1 << 5) 90*4882a593Smuzhiyun #define MSR_CTS (1 << 4) 91*4882a593Smuzhiyun #define MSR_DDCD (1 << 3) 92*4882a593Smuzhiyun #define MSR_TERI (1 << 2) 93*4882a593Smuzhiyun #define MSR_DDSR (1 << 1) 94*4882a593Smuzhiyun #define MSR_DCTS (1 << 0) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif /* __REGS_UART_H__ */ 97