1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __REGS_MMC_H__ 8*4882a593Smuzhiyun #define __REGS_MMC_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MMC0_BASE 0x41100000 11*4882a593Smuzhiyun #define MMC1_BASE 0x42000000 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun int pxa_mmc_register(int card_index); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct pxa_mmc_regs { 16*4882a593Smuzhiyun uint32_t strpcl; 17*4882a593Smuzhiyun uint32_t stat; 18*4882a593Smuzhiyun uint32_t clkrt; 19*4882a593Smuzhiyun uint32_t spi; 20*4882a593Smuzhiyun uint32_t cmdat; 21*4882a593Smuzhiyun uint32_t resto; 22*4882a593Smuzhiyun uint32_t rdto; 23*4882a593Smuzhiyun uint32_t blklen; 24*4882a593Smuzhiyun uint32_t nob; 25*4882a593Smuzhiyun uint32_t prtbuf; 26*4882a593Smuzhiyun uint32_t i_mask; 27*4882a593Smuzhiyun uint32_t i_reg; 28*4882a593Smuzhiyun uint32_t cmd; 29*4882a593Smuzhiyun uint32_t argh; 30*4882a593Smuzhiyun uint32_t argl; 31*4882a593Smuzhiyun uint32_t res; 32*4882a593Smuzhiyun uint32_t rxfifo; 33*4882a593Smuzhiyun uint32_t txfifo; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* MMC_STRPCL */ 37*4882a593Smuzhiyun #define MMC_STRPCL_STOP_CLK (1 << 0) 38*4882a593Smuzhiyun #define MMC_STRPCL_START_CLK (1 << 1) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* MMC_STAT */ 41*4882a593Smuzhiyun #define MMC_STAT_END_CMD_RES (1 << 13) 42*4882a593Smuzhiyun #define MMC_STAT_PRG_DONE (1 << 12) 43*4882a593Smuzhiyun #define MMC_STAT_DATA_TRAN_DONE (1 << 11) 44*4882a593Smuzhiyun #define MMC_STAT_CLK_EN (1 << 8) 45*4882a593Smuzhiyun #define MMC_STAT_RECV_FIFO_FULL (1 << 7) 46*4882a593Smuzhiyun #define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) 47*4882a593Smuzhiyun #define MMC_STAT_RES_CRC_ERROR (1 << 5) 48*4882a593Smuzhiyun #define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) 49*4882a593Smuzhiyun #define MMC_STAT_CRC_READ_ERROR (1 << 3) 50*4882a593Smuzhiyun #define MMC_STAT_CRC_WRITE_ERROR (1 << 2) 51*4882a593Smuzhiyun #define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) 52*4882a593Smuzhiyun #define MMC_STAT_READ_TIME_OUT (1 << 0) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* MMC_CLKRT */ 55*4882a593Smuzhiyun #define MMC_CLKRT_20MHZ 0 56*4882a593Smuzhiyun #define MMC_CLKRT_10MHZ 1 57*4882a593Smuzhiyun #define MMC_CLKRT_5MHZ 2 58*4882a593Smuzhiyun #define MMC_CLKRT_2_5MHZ 3 59*4882a593Smuzhiyun #define MMC_CLKRT_1_25MHZ 4 60*4882a593Smuzhiyun #define MMC_CLKRT_0_625MHZ 5 61*4882a593Smuzhiyun #define MMC_CLKRT_0_3125MHZ 6 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* MMC_SPI */ 64*4882a593Smuzhiyun #define MMC_SPI_EN (1 << 0) 65*4882a593Smuzhiyun #define MMC_SPI_CS_EN (1 << 2) 66*4882a593Smuzhiyun #define MMC_SPI_CS_ADDRESS (1 << 3) 67*4882a593Smuzhiyun #define MMC_SPI_CRC_ON (1 << 1) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* MMC_CMDAT */ 70*4882a593Smuzhiyun #define MMC_CMDAT_SD_4DAT (1 << 8) 71*4882a593Smuzhiyun #define MMC_CMDAT_MMC_DMA_EN (1 << 7) 72*4882a593Smuzhiyun #define MMC_CMDAT_INIT (1 << 6) 73*4882a593Smuzhiyun #define MMC_CMDAT_BUSY (1 << 5) 74*4882a593Smuzhiyun #define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) 75*4882a593Smuzhiyun #define MMC_CMDAT_STREAM (1 << 4) 76*4882a593Smuzhiyun #define MMC_CMDAT_WRITE (1 << 3) 77*4882a593Smuzhiyun #define MMC_CMDAT_DATA_EN (1 << 2) 78*4882a593Smuzhiyun #define MMC_CMDAT_R0 0 79*4882a593Smuzhiyun #define MMC_CMDAT_R1 1 80*4882a593Smuzhiyun #define MMC_CMDAT_R2 2 81*4882a593Smuzhiyun #define MMC_CMDAT_R3 3 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* MMC_RESTO */ 84*4882a593Smuzhiyun #define MMC_RES_TO_MAX_MASK 0x7f 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* MMC_RDTO */ 87*4882a593Smuzhiyun #define MMC_READ_TO_MAX_MASK 0xffff 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* MMC_BLKLEN */ 90*4882a593Smuzhiyun #define MMC_BLK_LEN_MAX_MASK 0x3ff 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* MMC_PRTBUF */ 93*4882a593Smuzhiyun #define MMC_PRTBUF_BUF_PART_FULL (1 << 0) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* MMC_I_MASK */ 96*4882a593Smuzhiyun #define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) 97*4882a593Smuzhiyun #define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) 98*4882a593Smuzhiyun #define MMC_I_MASK_CLK_IS_OFF (1 << 4) 99*4882a593Smuzhiyun #define MMC_I_MASK_STOP_CMD (1 << 3) 100*4882a593Smuzhiyun #define MMC_I_MASK_END_CMD_RES (1 << 2) 101*4882a593Smuzhiyun #define MMC_I_MASK_PRG_DONE (1 << 1) 102*4882a593Smuzhiyun #define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) 103*4882a593Smuzhiyun #define MMC_I_MASK_ALL 0x7f 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* MMC_I_REG */ 107*4882a593Smuzhiyun #define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) 108*4882a593Smuzhiyun #define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) 109*4882a593Smuzhiyun #define MMC_I_REG_CLK_IS_OFF (1 << 4) 110*4882a593Smuzhiyun #define MMC_I_REG_STOP_CMD (1 << 3) 111*4882a593Smuzhiyun #define MMC_I_REG_END_CMD_RES (1 << 2) 112*4882a593Smuzhiyun #define MMC_I_REG_PRG_DONE (1 << 1) 113*4882a593Smuzhiyun #define MMC_I_REG_DATA_TRAN_DONE (1 << 0) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* MMC_CMD */ 116*4882a593Smuzhiyun #define MMC_CMD_INDEX_MAX 0x6f 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define MMC_R1_IDLE_STATE 0x01 119*4882a593Smuzhiyun #define MMC_R1_ERASE_STATE 0x02 120*4882a593Smuzhiyun #define MMC_R1_ILLEGAL_CMD 0x04 121*4882a593Smuzhiyun #define MMC_R1_COM_CRC_ERR 0x08 122*4882a593Smuzhiyun #define MMC_R1_ERASE_SEQ_ERR 0x01 123*4882a593Smuzhiyun #define MMC_R1_ADDR_ERR 0x02 124*4882a593Smuzhiyun #define MMC_R1_PARAM_ERR 0x04 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define MMC_R1B_WP_ERASE_SKIP 0x0002 127*4882a593Smuzhiyun #define MMC_R1B_ERR 0x0004 128*4882a593Smuzhiyun #define MMC_R1B_CC_ERR 0x0008 129*4882a593Smuzhiyun #define MMC_R1B_CARD_ECC_ERR 0x0010 130*4882a593Smuzhiyun #define MMC_R1B_WP_VIOLATION 0x0020 131*4882a593Smuzhiyun #define MMC_R1B_ERASE_PARAM 0x0040 132*4882a593Smuzhiyun #define MMC_R1B_OOR 0x0080 133*4882a593Smuzhiyun #define MMC_R1B_IDLE_STATE 0x0100 134*4882a593Smuzhiyun #define MMC_R1B_ERASE_RESET 0x0200 135*4882a593Smuzhiyun #define MMC_R1B_ILLEGAL_CMD 0x0400 136*4882a593Smuzhiyun #define MMC_R1B_COM_CRC_ERR 0x0800 137*4882a593Smuzhiyun #define MMC_R1B_ERASE_SEQ_ERR 0x1000 138*4882a593Smuzhiyun #define MMC_R1B_ADDR_ERR 0x2000 139*4882a593Smuzhiyun #define MMC_R1B_PARAM_ERR 0x4000 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __REGS_MMC_H__ */ 142