1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _SYS_PROTO_H_
9*4882a593Smuzhiyun #define _SYS_PROTO_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/arch/omap.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/clock.h>
14*4882a593Smuzhiyun #include <asm/omap_common.h>
15*4882a593Smuzhiyun #include <linux/mtd/omap_gpmc.h>
16*4882a593Smuzhiyun #include <asm/arch/clock.h>
17*4882a593Smuzhiyun #include <asm/ti-common/sys_proto.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * Structure for Iodelay configuration registers.
23*4882a593Smuzhiyun * Theoretical max for g_delay is 21560 ps.
24*4882a593Smuzhiyun * Theoretical max for a_delay is 1/3rd of g_delay max.
25*4882a593Smuzhiyun * So using u16 for both a/g_delay.
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun struct iodelay_cfg_entry {
28*4882a593Smuzhiyun u16 offset;
29*4882a593Smuzhiyun u16 a_delay;
30*4882a593Smuzhiyun u16 g_delay;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct pad_conf_entry {
34*4882a593Smuzhiyun u32 offset;
35*4882a593Smuzhiyun u32 val;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct omap_sysinfo {
39*4882a593Smuzhiyun char *board_string;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun extern const struct omap_sysinfo sysinfo;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun void gpmc_init(void);
44*4882a593Smuzhiyun void watchdog_init(void);
45*4882a593Smuzhiyun u32 get_device_type(void);
46*4882a593Smuzhiyun void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
47*4882a593Smuzhiyun void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
48*4882a593Smuzhiyun void set_muxconf_regs(void);
49*4882a593Smuzhiyun u32 wait_on_value(u32, u32, void *, u32);
50*4882a593Smuzhiyun void sdelay(unsigned long);
51*4882a593Smuzhiyun void setup_early_clocks(void);
52*4882a593Smuzhiyun void prcm_init(void);
53*4882a593Smuzhiyun void do_board_detect(void);
54*4882a593Smuzhiyun void vcores_init(void);
55*4882a593Smuzhiyun void bypass_dpll(u32 const base);
56*4882a593Smuzhiyun void freq_update_core(void);
57*4882a593Smuzhiyun u32 get_sys_clk_freq(void);
58*4882a593Smuzhiyun u32 omap5_ddr_clk(void);
59*4882a593Smuzhiyun void cancel_out(u32 *num, u32 *den, u32 den_limit);
60*4882a593Smuzhiyun void sdram_init(void);
61*4882a593Smuzhiyun u32 omap_sdram_size(void);
62*4882a593Smuzhiyun u32 cortex_rev(void);
63*4882a593Smuzhiyun void save_omap_boot_params(void);
64*4882a593Smuzhiyun void init_omap_revision(void);
65*4882a593Smuzhiyun void do_io_settings(void);
66*4882a593Smuzhiyun void sri2c_init(void);
67*4882a593Smuzhiyun int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
68*4882a593Smuzhiyun u32 warm_reset(void);
69*4882a593Smuzhiyun void force_emif_self_refresh(void);
70*4882a593Smuzhiyun void get_ioregs(const struct ctrl_ioregs **regs);
71*4882a593Smuzhiyun void srcomp_enable(void);
72*4882a593Smuzhiyun void setup_warmreset_time(void);
73*4882a593Smuzhiyun
div_round_up(u32 num,u32 den)74*4882a593Smuzhiyun static inline u32 div_round_up(u32 num, u32 den)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun return (num + den - 1)/den;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
usec_to_32k(u32 usec)79*4882a593Smuzhiyun static inline u32 usec_to_32k(u32 usec)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return div_round_up(32768 * usec, 1000000);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define OMAP5_SERVICE_L2ACTLR_SET 0x104
85*4882a593Smuzhiyun #define OMAP5_SERVICE_ACR_SET 0x107
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #endif
88