1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SATA Wrapper Register map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2013 5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _TI_SATA_H 11*4882a593Smuzhiyun #define _TI_SATA_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* SATA Wrapper module */ 14*4882a593Smuzhiyun #define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) 15*4882a593Smuzhiyun /* SATA PHY Module */ 16*4882a593Smuzhiyun #define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SATA Wrapper register offsets */ 19*4882a593Smuzhiyun #define TI_SATA_SYSCONFIG 0x00 20*4882a593Smuzhiyun #define TI_SATA_CDRLOCK 0x04 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Register Set */ 23*4882a593Smuzhiyun #define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) 24*4882a593Smuzhiyun #define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) 25*4882a593Smuzhiyun #define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Standby modes */ 28*4882a593Smuzhiyun #define TI_SATA_STANDBY_FORCE 0x0 29*4882a593Smuzhiyun #define TI_SATA_STANDBY_NO (0x1 << 4) 30*4882a593Smuzhiyun #define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) 31*4882a593Smuzhiyun #define TI_SATA_STANDBY_SMART (0x2 << 4) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Idle modes */ 34*4882a593Smuzhiyun #define TI_SATA_IDLE_FORCE 0x0 35*4882a593Smuzhiyun #define TI_SATA_IDLE_NO (0x1 << 2) 36*4882a593Smuzhiyun #define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) 37*4882a593Smuzhiyun #define TI_SATA_IDLE_SMART (0x2 << 2) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* _TI_SATA_H */ 40