1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004-2009 3*4882a593Smuzhiyun * Texas Instruments Incorporated 4*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 5*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 6*4882a593Smuzhiyun * Balaji Krishnamoorthy <balajitk@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _MUX_OMAP5_H_ 11*4882a593Smuzhiyun #define _MUX_OMAP5_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifdef CONFIG_OFF_PADCONF 16*4882a593Smuzhiyun #define OFF_PD (1 << 12) 17*4882a593Smuzhiyun #define OFF_PU (3 << 12) 18*4882a593Smuzhiyun #define OFF_OUT_PTD (0 << 10) 19*4882a593Smuzhiyun #define OFF_OUT_PTU (2 << 10) 20*4882a593Smuzhiyun #define OFF_IN (1 << 10) 21*4882a593Smuzhiyun #define OFF_OUT (0 << 10) 22*4882a593Smuzhiyun #define OFF_EN (1 << 9) 23*4882a593Smuzhiyun #else 24*4882a593Smuzhiyun #define OFF_PD (0 << 12) 25*4882a593Smuzhiyun #define OFF_PU (0 << 12) 26*4882a593Smuzhiyun #define OFF_OUT_PTD (0 << 10) 27*4882a593Smuzhiyun #define OFF_OUT_PTU (0 << 10) 28*4882a593Smuzhiyun #define OFF_IN (0 << 10) 29*4882a593Smuzhiyun #define OFF_OUT (0 << 10) 30*4882a593Smuzhiyun #define OFF_EN (0 << 9) 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define IEN (1 << 8) 34*4882a593Smuzhiyun #define IDIS (0 << 8) 35*4882a593Smuzhiyun #define PTU (3 << 3) 36*4882a593Smuzhiyun #define PTD (1 << 3) 37*4882a593Smuzhiyun #define EN (1 << 3) 38*4882a593Smuzhiyun #define DIS (0 << 3) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define M0 0 41*4882a593Smuzhiyun #define M1 1 42*4882a593Smuzhiyun #define M2 2 43*4882a593Smuzhiyun #define M3 3 44*4882a593Smuzhiyun #define M4 4 45*4882a593Smuzhiyun #define M5 5 46*4882a593Smuzhiyun #define M6 6 47*4882a593Smuzhiyun #define M7 7 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define SAFE_MODE M7 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifdef CONFIG_OFF_PADCONF 52*4882a593Smuzhiyun #define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) 53*4882a593Smuzhiyun #define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) 54*4882a593Smuzhiyun #define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) 55*4882a593Smuzhiyun #define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) 56*4882a593Smuzhiyun #else 57*4882a593Smuzhiyun #define OFF_IN_PD 0 58*4882a593Smuzhiyun #define OFF_IN_PU 0 59*4882a593Smuzhiyun #define OFF_OUT_PD 0 60*4882a593Smuzhiyun #define OFF_OUT_PU 0 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CORE_REVISION 0x0000 64*4882a593Smuzhiyun #define CORE_HWINFO 0x0004 65*4882a593Smuzhiyun #define CORE_SYSCONFIG 0x0010 66*4882a593Smuzhiyun #define EMMC_CLK 0x0040 67*4882a593Smuzhiyun #define EMMC_CMD 0x0042 68*4882a593Smuzhiyun #define EMMC_DATA0 0x0044 69*4882a593Smuzhiyun #define EMMC_DATA1 0x0046 70*4882a593Smuzhiyun #define EMMC_DATA2 0x0048 71*4882a593Smuzhiyun #define EMMC_DATA3 0x004a 72*4882a593Smuzhiyun #define EMMC_DATA4 0x004c 73*4882a593Smuzhiyun #define EMMC_DATA5 0x004e 74*4882a593Smuzhiyun #define EMMC_DATA6 0x0050 75*4882a593Smuzhiyun #define EMMC_DATA7 0x0052 76*4882a593Smuzhiyun #define C2C_CLKOUT0 0x0054 77*4882a593Smuzhiyun #define C2C_CLKOUT1 0x0056 78*4882a593Smuzhiyun #define C2C_CLKIN0 0x0058 79*4882a593Smuzhiyun #define C2C_CLKIN1 0x005a 80*4882a593Smuzhiyun #define C2C_DATAIN0 0x005c 81*4882a593Smuzhiyun #define C2C_DATAIN1 0x005e 82*4882a593Smuzhiyun #define C2C_DATAIN2 0x0060 83*4882a593Smuzhiyun #define C2C_DATAIN3 0x0062 84*4882a593Smuzhiyun #define C2C_DATAIN4 0x0064 85*4882a593Smuzhiyun #define C2C_DATAIN5 0x0066 86*4882a593Smuzhiyun #define C2C_DATAIN6 0x0068 87*4882a593Smuzhiyun #define C2C_DATAIN7 0x006a 88*4882a593Smuzhiyun #define C2C_DATAOUT0 0x006c 89*4882a593Smuzhiyun #define C2C_DATAOUT1 0x006e 90*4882a593Smuzhiyun #define C2C_DATAOUT2 0x0070 91*4882a593Smuzhiyun #define C2C_DATAOUT3 0x0072 92*4882a593Smuzhiyun #define C2C_DATAOUT4 0x0074 93*4882a593Smuzhiyun #define C2C_DATAOUT5 0x0076 94*4882a593Smuzhiyun #define C2C_DATAOUT6 0x0078 95*4882a593Smuzhiyun #define C2C_DATAOUT7 0x007a 96*4882a593Smuzhiyun #define C2C_DATA8 0x007c 97*4882a593Smuzhiyun #define C2C_DATA9 0x007e 98*4882a593Smuzhiyun #define C2C_DATA10 0x0080 99*4882a593Smuzhiyun #define C2C_DATA11 0x0082 100*4882a593Smuzhiyun #define C2C_DATA12 0x0084 101*4882a593Smuzhiyun #define C2C_DATA13 0x0086 102*4882a593Smuzhiyun #define C2C_DATA14 0x0088 103*4882a593Smuzhiyun #define C2C_DATA15 0x008a 104*4882a593Smuzhiyun #define LLIA_WAKEREQOUT 0x008c 105*4882a593Smuzhiyun #define LLIB_WAKEREQOUT 0x008e 106*4882a593Smuzhiyun #define HSI1_ACREADY 0x0090 107*4882a593Smuzhiyun #define HSI1_CAREADY 0x0092 108*4882a593Smuzhiyun #define HSI1_ACWAKE 0x0094 109*4882a593Smuzhiyun #define HSI1_CAWAKE 0x0096 110*4882a593Smuzhiyun #define HSI1_ACFLAG 0x0098 111*4882a593Smuzhiyun #define HSI1_ACDATA 0x009a 112*4882a593Smuzhiyun #define HSI1_CAFLAG 0x009c 113*4882a593Smuzhiyun #define HSI1_CADATA 0x009e 114*4882a593Smuzhiyun #define UART1_TX 0x00a0 115*4882a593Smuzhiyun #define UART1_CTS 0x00a2 116*4882a593Smuzhiyun #define UART1_RX 0x00a4 117*4882a593Smuzhiyun #define UART1_RTS 0x00a6 118*4882a593Smuzhiyun #define HSI2_CAREADY 0x00a8 119*4882a593Smuzhiyun #define HSI2_ACREADY 0x00aa 120*4882a593Smuzhiyun #define HSI2_CAWAKE 0x00ac 121*4882a593Smuzhiyun #define HSI2_ACWAKE 0x00ae 122*4882a593Smuzhiyun #define HSI2_CAFLAG 0x00b0 123*4882a593Smuzhiyun #define HSI2_CADATA 0x00b2 124*4882a593Smuzhiyun #define HSI2_ACFLAG 0x00b4 125*4882a593Smuzhiyun #define HSI2_ACDATA 0x00b6 126*4882a593Smuzhiyun #define UART2_RTS 0x00b8 127*4882a593Smuzhiyun #define UART2_CTS 0x00ba 128*4882a593Smuzhiyun #define UART2_RX 0x00bc 129*4882a593Smuzhiyun #define UART2_TX 0x00be 130*4882a593Smuzhiyun #define USBB1_HSIC_STROBE 0x00c0 131*4882a593Smuzhiyun #define USBB1_HSIC_DATA 0x00c2 132*4882a593Smuzhiyun #define USBB2_HSIC_STROBE 0x00c4 133*4882a593Smuzhiyun #define USBB2_HSIC_DATA 0x00c6 134*4882a593Smuzhiyun #define TIMER10_PWM_EVT 0x00c8 135*4882a593Smuzhiyun #define DSIPORTA_TE0 0x00ca 136*4882a593Smuzhiyun #define DSIPORTA_LANE0X 0x00cc 137*4882a593Smuzhiyun #define DSIPORTA_LANE0Y 0x00ce 138*4882a593Smuzhiyun #define DSIPORTA_LANE1X 0x00d0 139*4882a593Smuzhiyun #define DSIPORTA_LANE1Y 0x00d2 140*4882a593Smuzhiyun #define DSIPORTA_LANE2X 0x00d4 141*4882a593Smuzhiyun #define DSIPORTA_LANE2Y 0x00d6 142*4882a593Smuzhiyun #define DSIPORTA_LANE3X 0x00d8 143*4882a593Smuzhiyun #define DSIPORTA_LANE3Y 0x00da 144*4882a593Smuzhiyun #define DSIPORTA_LANE4X 0x00dc 145*4882a593Smuzhiyun #define DSIPORTA_LANE4Y 0x00de 146*4882a593Smuzhiyun #define DSIPORTC_LANE0X 0x00e0 147*4882a593Smuzhiyun #define DSIPORTC_LANE0Y 0x00e2 148*4882a593Smuzhiyun #define DSIPORTC_LANE1X 0x00e4 149*4882a593Smuzhiyun #define DSIPORTC_LANE1Y 0x00e6 150*4882a593Smuzhiyun #define DSIPORTC_LANE2X 0x00e8 151*4882a593Smuzhiyun #define DSIPORTC_LANE2Y 0x00ea 152*4882a593Smuzhiyun #define DSIPORTC_LANE3X 0x00ec 153*4882a593Smuzhiyun #define DSIPORTC_LANE3Y 0x00ee 154*4882a593Smuzhiyun #define DSIPORTC_LANE4X 0x00f0 155*4882a593Smuzhiyun #define DSIPORTC_LANE4Y 0x00f2 156*4882a593Smuzhiyun #define DSIPORTC_TE0 0x00f4 157*4882a593Smuzhiyun #define TIMER9_PWM_EVT 0x00f6 158*4882a593Smuzhiyun #define I2C4_SCL 0x00f8 159*4882a593Smuzhiyun #define I2C4_SDA 0x00fa 160*4882a593Smuzhiyun #define MCSPI2_CLK 0x00fc 161*4882a593Smuzhiyun #define MCSPI2_SIMO 0x00fe 162*4882a593Smuzhiyun #define MCSPI2_SOMI 0x0100 163*4882a593Smuzhiyun #define MCSPI2_CS0 0x0102 164*4882a593Smuzhiyun #define RFBI_DATA15 0x0104 165*4882a593Smuzhiyun #define RFBI_DATA14 0x0106 166*4882a593Smuzhiyun #define RFBI_DATA13 0x0108 167*4882a593Smuzhiyun #define RFBI_DATA12 0x010a 168*4882a593Smuzhiyun #define RFBI_DATA11 0x010c 169*4882a593Smuzhiyun #define RFBI_DATA10 0x010e 170*4882a593Smuzhiyun #define RFBI_DATA9 0x0110 171*4882a593Smuzhiyun #define RFBI_DATA8 0x0112 172*4882a593Smuzhiyun #define RFBI_DATA7 0x0114 173*4882a593Smuzhiyun #define RFBI_DATA6 0x0116 174*4882a593Smuzhiyun #define RFBI_DATA5 0x0118 175*4882a593Smuzhiyun #define RFBI_DATA4 0x011a 176*4882a593Smuzhiyun #define RFBI_DATA3 0x011c 177*4882a593Smuzhiyun #define RFBI_DATA2 0x011e 178*4882a593Smuzhiyun #define RFBI_DATA1 0x0120 179*4882a593Smuzhiyun #define RFBI_DATA0 0x0122 180*4882a593Smuzhiyun #define RFBI_WE 0x0124 181*4882a593Smuzhiyun #define RFBI_CS0 0x0126 182*4882a593Smuzhiyun #define RFBI_A0 0x0128 183*4882a593Smuzhiyun #define RFBI_RE 0x012a 184*4882a593Smuzhiyun #define RFBI_HSYNC0 0x012c 185*4882a593Smuzhiyun #define RFBI_TE_VSYNC0 0x012e 186*4882a593Smuzhiyun #define GPIO6_182 0x0130 187*4882a593Smuzhiyun #define GPIO6_183 0x0132 188*4882a593Smuzhiyun #define GPIO6_184 0x0134 189*4882a593Smuzhiyun #define GPIO6_185 0x0136 190*4882a593Smuzhiyun #define GPIO6_186 0x0138 191*4882a593Smuzhiyun #define GPIO6_187 0x013a 192*4882a593Smuzhiyun #define HDMI_CEC 0x013c 193*4882a593Smuzhiyun #define HDMI_HPD 0x013e 194*4882a593Smuzhiyun #define HDMI_DDC_SCL 0x0140 195*4882a593Smuzhiyun #define HDMI_DDC_SDA 0x0142 196*4882a593Smuzhiyun #define CSIPORTC_LANE0X 0x0144 197*4882a593Smuzhiyun #define CSIPORTC_LANE0Y 0x0146 198*4882a593Smuzhiyun #define CSIPORTC_LANE1X 0x0148 199*4882a593Smuzhiyun #define CSIPORTC_LANE1Y 0x014a 200*4882a593Smuzhiyun #define CSIPORTB_LANE0X 0x014c 201*4882a593Smuzhiyun #define CSIPORTB_LANE0Y 0x014e 202*4882a593Smuzhiyun #define CSIPORTB_LANE1X 0x0150 203*4882a593Smuzhiyun #define CSIPORTB_LANE1Y 0x0152 204*4882a593Smuzhiyun #define CSIPORTB_LANE2X 0x0154 205*4882a593Smuzhiyun #define CSIPORTB_LANE2Y 0x0156 206*4882a593Smuzhiyun #define CSIPORTA_LANE0X 0x0158 207*4882a593Smuzhiyun #define CSIPORTA_LANE0Y 0x015a 208*4882a593Smuzhiyun #define CSIPORTA_LANE1X 0x015c 209*4882a593Smuzhiyun #define CSIPORTA_LANE1Y 0x015e 210*4882a593Smuzhiyun #define CSIPORTA_LANE2X 0x0160 211*4882a593Smuzhiyun #define CSIPORTA_LANE2Y 0x0162 212*4882a593Smuzhiyun #define CSIPORTA_LANE3X 0x0164 213*4882a593Smuzhiyun #define CSIPORTA_LANE3Y 0x0166 214*4882a593Smuzhiyun #define CSIPORTA_LANE4X 0x0168 215*4882a593Smuzhiyun #define CSIPORTA_LANE4Y 0x016a 216*4882a593Smuzhiyun #define CAM_SHUTTER 0x016c 217*4882a593Smuzhiyun #define CAM_STROBE 0x016e 218*4882a593Smuzhiyun #define CAM_GLOBALRESET 0x0170 219*4882a593Smuzhiyun #define TIMER11_PWM_EVT 0x0172 220*4882a593Smuzhiyun #define TIMER5_PWM_EVT 0x0174 221*4882a593Smuzhiyun #define TIMER6_PWM_EVT 0x0176 222*4882a593Smuzhiyun #define TIMER8_PWM_EVT 0x0178 223*4882a593Smuzhiyun #define I2C3_SCL 0x017a 224*4882a593Smuzhiyun #define I2C3_SDA 0x017c 225*4882a593Smuzhiyun #define GPIO8_233 0x017e 226*4882a593Smuzhiyun #define GPIO8_234 0x0180 227*4882a593Smuzhiyun #define ABE_CLKS 0x0182 228*4882a593Smuzhiyun #define ABEDMIC_DIN1 0x0184 229*4882a593Smuzhiyun #define ABEDMIC_DIN2 0x0186 230*4882a593Smuzhiyun #define ABEDMIC_DIN3 0x0188 231*4882a593Smuzhiyun #define ABEDMIC_CLK1 0x018a 232*4882a593Smuzhiyun #define ABEDMIC_CLK2 0x018c 233*4882a593Smuzhiyun #define ABEDMIC_CLK3 0x018e 234*4882a593Smuzhiyun #define ABESLIMBUS1_CLOCK 0x0190 235*4882a593Smuzhiyun #define ABESLIMBUS1_DATA 0x0192 236*4882a593Smuzhiyun #define ABEMCBSP2_DR 0x0194 237*4882a593Smuzhiyun #define ABEMCBSP2_DX 0x0196 238*4882a593Smuzhiyun #define ABEMCBSP2_FSX 0x0198 239*4882a593Smuzhiyun #define ABEMCBSP2_CLKX 0x019a 240*4882a593Smuzhiyun #define ABEMCPDM_UL_DATA 0x019c 241*4882a593Smuzhiyun #define ABEMCPDM_DL_DATA 0x019e 242*4882a593Smuzhiyun #define ABEMCPDM_FRAME 0x01a0 243*4882a593Smuzhiyun #define ABEMCPDM_LB_CLK 0x01a2 244*4882a593Smuzhiyun #define WLSDIO_CLK 0x01a4 245*4882a593Smuzhiyun #define WLSDIO_CMD 0x01a6 246*4882a593Smuzhiyun #define WLSDIO_DATA0 0x01a8 247*4882a593Smuzhiyun #define WLSDIO_DATA1 0x01aa 248*4882a593Smuzhiyun #define WLSDIO_DATA2 0x01ac 249*4882a593Smuzhiyun #define WLSDIO_DATA3 0x01ae 250*4882a593Smuzhiyun #define UART5_RX 0x01b0 251*4882a593Smuzhiyun #define UART5_TX 0x01b2 252*4882a593Smuzhiyun #define UART5_CTS 0x01b4 253*4882a593Smuzhiyun #define UART5_RTS 0x01b6 254*4882a593Smuzhiyun #define I2C2_SCL 0x01b8 255*4882a593Smuzhiyun #define I2C2_SDA 0x01ba 256*4882a593Smuzhiyun #define MCSPI1_CLK 0x01bc 257*4882a593Smuzhiyun #define MCSPI1_SOMI 0x01be 258*4882a593Smuzhiyun #define MCSPI1_SIMO 0x01c0 259*4882a593Smuzhiyun #define MCSPI1_CS0 0x01c2 260*4882a593Smuzhiyun #define MCSPI1_CS1 0x01c4 261*4882a593Smuzhiyun #define I2C5_SCL 0x01c6 262*4882a593Smuzhiyun #define I2C5_SDA 0x01c8 263*4882a593Smuzhiyun #define PERSLIMBUS2_CLOCK 0x01ca 264*4882a593Smuzhiyun #define PERSLIMBUS2_DATA 0x01cc 265*4882a593Smuzhiyun #define UART6_TX 0x01ce 266*4882a593Smuzhiyun #define UART6_RX 0x01d0 267*4882a593Smuzhiyun #define UART6_CTS 0x01d2 268*4882a593Smuzhiyun #define UART6_RTS 0x01d4 269*4882a593Smuzhiyun #define UART3_CTS_RCTX 0x01d6 270*4882a593Smuzhiyun #define UART3_RTS_IRSD 0x01d8 271*4882a593Smuzhiyun #define UART3_TX_IRTX 0x01da 272*4882a593Smuzhiyun #define UART3_RX_IRRX 0x01dc 273*4882a593Smuzhiyun #define USBB3_HSIC_STROBE 0x01de 274*4882a593Smuzhiyun #define USBB3_HSIC_DATA 0x01e0 275*4882a593Smuzhiyun #define SDCARD_CLK 0x01e2 276*4882a593Smuzhiyun #define SDCARD_CMD 0x01e4 277*4882a593Smuzhiyun #define SDCARD_DATA2 0x01e6 278*4882a593Smuzhiyun #define SDCARD_DATA3 0x01e8 279*4882a593Smuzhiyun #define SDCARD_DATA0 0x01ea 280*4882a593Smuzhiyun #define SDCARD_DATA1 0x01ec 281*4882a593Smuzhiyun #define USBD0_HS_DP 0x01ee 282*4882a593Smuzhiyun #define USBD0_HS_DM 0x01f0 283*4882a593Smuzhiyun #define I2C1_PMIC_SCL 0x01f2 284*4882a593Smuzhiyun #define I2C1_PMIC_SDA 0x01f4 285*4882a593Smuzhiyun #define USBD0_SS_RX 0x01f6 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define LLIA_WAKEREQIN 0x0040 288*4882a593Smuzhiyun #define LLIB_WAKEREQIN 0x0042 289*4882a593Smuzhiyun #define DRM_EMU0 0x0044 290*4882a593Smuzhiyun #define DRM_EMU1 0x0046 291*4882a593Smuzhiyun #define JTAG_NTRST 0x0048 292*4882a593Smuzhiyun #define JTAG_TCK 0x004a 293*4882a593Smuzhiyun #define JTAG_RTCK 0x004c 294*4882a593Smuzhiyun #define JTAG_TMSC 0x004e 295*4882a593Smuzhiyun #define JTAG_TDI 0x0050 296*4882a593Smuzhiyun #define JTAG_TDO 0x0052 297*4882a593Smuzhiyun #define SYS_32K 0x0054 298*4882a593Smuzhiyun #define FREF_CLK_IOREQ 0x0056 299*4882a593Smuzhiyun #define FREF_CLK0_OUT 0x0058 300*4882a593Smuzhiyun #define FREF_CLK1_OUT 0x005a 301*4882a593Smuzhiyun #define FREF_CLK2_OUT 0x005c 302*4882a593Smuzhiyun #define FREF_CLK2_REQ 0x005e 303*4882a593Smuzhiyun #define FREF_CLK1_REQ 0x0060 304*4882a593Smuzhiyun #define SYS_NRESPWRON 0x0062 305*4882a593Smuzhiyun #define SYS_NRESWARM 0x0064 306*4882a593Smuzhiyun #define SYS_PWR_REQ 0x0066 307*4882a593Smuzhiyun #define SYS_NIRQ1 0x0068 308*4882a593Smuzhiyun #define SYS_NIRQ2 0x006a 309*4882a593Smuzhiyun #define SR_PMIC_SCL 0x006c 310*4882a593Smuzhiyun #define SR_PMIC_SDA 0x006e 311*4882a593Smuzhiyun #define SYS_BOOT0 0x0070 312*4882a593Smuzhiyun #define SYS_BOOT1 0x0072 313*4882a593Smuzhiyun #define SYS_BOOT2 0x0074 314*4882a593Smuzhiyun #define SYS_BOOT3 0x0076 315*4882a593Smuzhiyun #define SYS_BOOT4 0x0078 316*4882a593Smuzhiyun #define SYS_BOOT5 0x007a 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun #endif /* _MUX_OMAP5_H_ */ 319