1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 3*4882a593Smuzhiyun * Texas Instruments Incorporated 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Lokesh Vutla <lokeshvutla@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DRA7_IODELAY_H_ 11*4882a593Smuzhiyun #define _DRA7_IODELAY_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* CONFIG_REG_0 */ 17*4882a593Smuzhiyun #define CFG_REG_0_OFFSET 0xC 18*4882a593Smuzhiyun #define CFG_REG_ROM_READ_SHIFT 1 19*4882a593Smuzhiyun #define CFG_REG_ROM_READ_MASK (1 << 1) 20*4882a593Smuzhiyun #define CFG_REG_CALIB_STRT_SHIFT 0 21*4882a593Smuzhiyun #define CFG_REG_CALIB_STRT_MASK (1 << 0) 22*4882a593Smuzhiyun #define CFG_REG_CALIB_STRT 1 23*4882a593Smuzhiyun #define CFG_REG_CALIB_END 0 24*4882a593Smuzhiyun #define CFG_REG_ROM_READ_START (1 << 1) 25*4882a593Smuzhiyun #define CFG_REG_ROM_READ_END (0 << 1) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* CONFIG_REG_2 */ 28*4882a593Smuzhiyun #define CFG_REG_2_OFFSET 0x14 29*4882a593Smuzhiyun #define CFG_REG_REFCLK_PERIOD_SHIFT 0 30*4882a593Smuzhiyun #define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) 31*4882a593Smuzhiyun #define CFG_REG_REFCLK_PERIOD 0x2EF 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* CONFIG_REG_8 */ 34*4882a593Smuzhiyun #define CFG_REG_8_OFFSET 0x2C 35*4882a593Smuzhiyun #define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA 36*4882a593Smuzhiyun #define CFG_IODELAY_LOCK_KEY 0x0000AAAB 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* CONFIG_REG_3/4 */ 39*4882a593Smuzhiyun #define CFG_REG_3_OFFSET 0x18 40*4882a593Smuzhiyun #define CFG_REG_4_OFFSET 0x1C 41*4882a593Smuzhiyun #define CFG_REG_DLY_CNT_SHIFT 16 42*4882a593Smuzhiyun #define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) 43*4882a593Smuzhiyun #define CFG_REG_REF_CNT_SHIFT 0 44*4882a593Smuzhiyun #define CFG_REG_REF_CNT_MASK (0xFFFF << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* CTRL_CORE_SMA_SW_0 */ 47*4882a593Smuzhiyun #define CTRL_ISOLATE_SHIFT 2 48*4882a593Smuzhiyun #define CTRL_ISOLATE_MASK (1 << 2) 49*4882a593Smuzhiyun #define ISOLATE_IO 1 50*4882a593Smuzhiyun #define DEISOLATE_IO 0 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* CTRL_CORE_SMA_SW_1 */ 53*4882a593Smuzhiyun #define RGMII2_ID_MODE_N_MASK (1 << 26) 54*4882a593Smuzhiyun #define RGMII1_ID_MODE_N_MASK (1 << 25) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* PRM_IO_PMCTRL */ 57*4882a593Smuzhiyun #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 58*4882a593Smuzhiyun #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) 59*4882a593Smuzhiyun #define PMCTRL_ISOCLK_STATUS_SHIFT 1 60*4882a593Smuzhiyun #define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) 61*4882a593Smuzhiyun #define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 62*4882a593Smuzhiyun #define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define ERR_CALIBRATE_IODELAY 0x1 65*4882a593Smuzhiyun #define ERR_DEISOLATE_IO 0x2 66*4882a593Smuzhiyun #define ERR_ISOLATE_IO 0x4 67*4882a593Smuzhiyun #define ERR_UPDATE_DELAY 0x8 68*4882a593Smuzhiyun #define ERR_CPDE 0x3 69*4882a593Smuzhiyun #define ERR_FPDE 0x5 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* CFG_XXX */ 72*4882a593Smuzhiyun #define CFG_X_SIGNATURE_SHIFT 12 73*4882a593Smuzhiyun #define CFG_X_SIGNATURE_MASK (0x3F << 12) 74*4882a593Smuzhiyun #define CFG_X_LOCK_SHIFT 10 75*4882a593Smuzhiyun #define CFG_X_LOCK_MASK (0x1 << 10) 76*4882a593Smuzhiyun #define CFG_X_COARSE_DLY_SHIFT 5 77*4882a593Smuzhiyun #define CFG_X_COARSE_DLY_MASK (0x1F << 5) 78*4882a593Smuzhiyun #define CFG_X_FINE_DLY_SHIFT 0 79*4882a593Smuzhiyun #define CFG_X_FINE_DLY_MASK (0x1F << 0) 80*4882a593Smuzhiyun #define CFG_X_SIGNATURE 0x29 81*4882a593Smuzhiyun #define CFG_X_LOCK 1 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, 84*4882a593Smuzhiyun struct iodelay_cfg_entry const *iodelay, 85*4882a593Smuzhiyun int niodelays); 86*4882a593Smuzhiyun int __recalibrate_iodelay_start(void); 87*4882a593Smuzhiyun void __recalibrate_iodelay_end(int ret); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, 90*4882a593Smuzhiyun int niodelays); 91*4882a593Smuzhiyun #endif 92