1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SYS_PROTO_H_ 9*4882a593Smuzhiyun #define _SYS_PROTO_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch/omap.h> 12*4882a593Smuzhiyun #include <asm/arch/clock.h> 13*4882a593Smuzhiyun #include <asm/io.h> 14*4882a593Smuzhiyun #include <asm/omap_common.h> 15*4882a593Smuzhiyun #include <linux/mtd/omap_gpmc.h> 16*4882a593Smuzhiyun #include <asm/arch/mux_omap4.h> 17*4882a593Smuzhiyun #include <asm/ti-common/sys_proto.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 22*4882a593Smuzhiyun extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; 23*4882a593Smuzhiyun extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; 24*4882a593Smuzhiyun extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; 25*4882a593Smuzhiyun extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; 26*4882a593Smuzhiyun extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; 27*4882a593Smuzhiyun extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; 28*4882a593Smuzhiyun extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; 29*4882a593Smuzhiyun #else 30*4882a593Smuzhiyun extern const struct lpddr2_device_details elpida_2G_S4_details; 31*4882a593Smuzhiyun extern const struct lpddr2_device_details elpida_4G_S4_details; 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 35*4882a593Smuzhiyun extern const struct lpddr2_device_timings jedec_default_timings; 36*4882a593Smuzhiyun #else 37*4882a593Smuzhiyun extern const struct lpddr2_device_timings elpida_2G_S4_timings; 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct omap_sysinfo { 41*4882a593Smuzhiyun char *board_string; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun extern const struct omap_sysinfo sysinfo; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void gpmc_init(void); 46*4882a593Smuzhiyun void watchdog_init(void); 47*4882a593Smuzhiyun u32 get_device_type(void); 48*4882a593Smuzhiyun void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); 49*4882a593Smuzhiyun void set_muxconf_regs(void); 50*4882a593Smuzhiyun u32 wait_on_value(u32, u32, void *, u32); 51*4882a593Smuzhiyun void sdelay(unsigned long); 52*4882a593Smuzhiyun void setup_early_clocks(void); 53*4882a593Smuzhiyun void prcm_init(void); 54*4882a593Smuzhiyun void do_board_detect(void); 55*4882a593Smuzhiyun void bypass_dpll(u32 const base); 56*4882a593Smuzhiyun void freq_update_core(void); 57*4882a593Smuzhiyun u32 get_sys_clk_freq(void); 58*4882a593Smuzhiyun u32 omap4_ddr_clk(void); 59*4882a593Smuzhiyun void cancel_out(u32 *num, u32 *den, u32 den_limit); 60*4882a593Smuzhiyun void sdram_init(void); 61*4882a593Smuzhiyun u32 omap_sdram_size(void); 62*4882a593Smuzhiyun u32 cortex_rev(void); 63*4882a593Smuzhiyun void save_omap_boot_params(void); 64*4882a593Smuzhiyun void init_omap_revision(void); 65*4882a593Smuzhiyun void do_io_settings(void); 66*4882a593Smuzhiyun void sri2c_init(void); 67*4882a593Smuzhiyun int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); 68*4882a593Smuzhiyun u32 warm_reset(void); 69*4882a593Smuzhiyun void force_emif_self_refresh(void); 70*4882a593Smuzhiyun void setup_warmreset_time(void); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75