1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2006-2010 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CPU_H 9*4882a593Smuzhiyun #define _CPU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 12*4882a593Smuzhiyun #include <asm/types.h> 13*4882a593Smuzhiyun #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/arch/hardware.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __KERNEL_STRICT_NAMES 18*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 19*4882a593Smuzhiyun struct gptimer { 20*4882a593Smuzhiyun u32 tidr; /* 0x00 r */ 21*4882a593Smuzhiyun u8 res[0xc]; 22*4882a593Smuzhiyun u32 tiocp_cfg; /* 0x10 rw */ 23*4882a593Smuzhiyun u32 tistat; /* 0x14 r */ 24*4882a593Smuzhiyun u32 tisr; /* 0x18 rw */ 25*4882a593Smuzhiyun u32 tier; /* 0x1c rw */ 26*4882a593Smuzhiyun u32 twer; /* 0x20 rw */ 27*4882a593Smuzhiyun u32 tclr; /* 0x24 rw */ 28*4882a593Smuzhiyun u32 tcrr; /* 0x28 rw */ 29*4882a593Smuzhiyun u32 tldr; /* 0x2c rw */ 30*4882a593Smuzhiyun u32 ttgr; /* 0x30 rw */ 31*4882a593Smuzhiyun u32 twpc; /* 0x34 r */ 32*4882a593Smuzhiyun u32 tmar; /* 0x38 rw */ 33*4882a593Smuzhiyun u32 tcar1; /* 0x3c r */ 34*4882a593Smuzhiyun u32 tcicr; /* 0x40 rw */ 35*4882a593Smuzhiyun u32 tcar2; /* 0x44 r */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 38*4882a593Smuzhiyun #endif /* __KERNEL_STRICT_NAMES */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* enable sys_clk NO-prescale /1 */ 41*4882a593Smuzhiyun #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Watchdog */ 44*4882a593Smuzhiyun #ifndef __KERNEL_STRICT_NAMES 45*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 46*4882a593Smuzhiyun struct watchdog { 47*4882a593Smuzhiyun u8 res1[0x34]; 48*4882a593Smuzhiyun u32 wwps; /* 0x34 r */ 49*4882a593Smuzhiyun u8 res2[0x10]; 50*4882a593Smuzhiyun u32 wspr; /* 0x48 rw */ 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 53*4882a593Smuzhiyun #endif /* __KERNEL_STRICT_NAMES */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define WD_UNLOCK1 0xAAAA 56*4882a593Smuzhiyun #define WD_UNLOCK2 0x5555 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define TCLR_ST (0x1 << 0) 59*4882a593Smuzhiyun #define TCLR_AR (0x1 << 1) 60*4882a593Smuzhiyun #define TCLR_PRE (0x1 << 5) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* I2C base */ 63*4882a593Smuzhiyun #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) 64*4882a593Smuzhiyun #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) 65*4882a593Smuzhiyun #define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) 66*4882a593Smuzhiyun #define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* MUSB base */ 69*4882a593Smuzhiyun #define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* OMAP4 GPIO registers */ 72*4882a593Smuzhiyun #define OMAP_GPIO_REVISION 0x0000 73*4882a593Smuzhiyun #define OMAP_GPIO_SYSCONFIG 0x0010 74*4882a593Smuzhiyun #define OMAP_GPIO_SYSSTATUS 0x0114 75*4882a593Smuzhiyun #define OMAP_GPIO_IRQSTATUS1 0x0118 76*4882a593Smuzhiyun #define OMAP_GPIO_IRQSTATUS2 0x0128 77*4882a593Smuzhiyun #define OMAP_GPIO_IRQENABLE2 0x012c 78*4882a593Smuzhiyun #define OMAP_GPIO_IRQENABLE1 0x011c 79*4882a593Smuzhiyun #define OMAP_GPIO_WAKE_EN 0x0120 80*4882a593Smuzhiyun #define OMAP_GPIO_CTRL 0x0130 81*4882a593Smuzhiyun #define OMAP_GPIO_OE 0x0134 82*4882a593Smuzhiyun #define OMAP_GPIO_DATAIN 0x0138 83*4882a593Smuzhiyun #define OMAP_GPIO_DATAOUT 0x013c 84*4882a593Smuzhiyun #define OMAP_GPIO_LEVELDETECT0 0x0140 85*4882a593Smuzhiyun #define OMAP_GPIO_LEVELDETECT1 0x0144 86*4882a593Smuzhiyun #define OMAP_GPIO_RISINGDETECT 0x0148 87*4882a593Smuzhiyun #define OMAP_GPIO_FALLINGDETECT 0x014c 88*4882a593Smuzhiyun #define OMAP_GPIO_DEBOUNCE_EN 0x0150 89*4882a593Smuzhiyun #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 90*4882a593Smuzhiyun #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 91*4882a593Smuzhiyun #define OMAP_GPIO_SETIRQENABLE1 0x0164 92*4882a593Smuzhiyun #define OMAP_GPIO_CLEARWKUENA 0x0180 93*4882a593Smuzhiyun #define OMAP_GPIO_SETWKUENA 0x0184 94*4882a593Smuzhiyun #define OMAP_GPIO_CLEARDATAOUT 0x0190 95*4882a593Smuzhiyun #define OMAP_GPIO_SETDATAOUT 0x0194 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * PRCM 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* PRM */ 102*4882a593Smuzhiyun #define PRM_BASE 0x4A306000 103*4882a593Smuzhiyun #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define PRM_RSTCTRL PRM_DEVICE_BASE 106*4882a593Smuzhiyun #define PRM_RSTCTRL_RESET 0x01 107*4882a593Smuzhiyun #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 108*4882a593Smuzhiyun #define PRM_RSTST_WARM_RESET_MASK 0x07EA 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif /* _CPU_H */ 111