1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004-2008 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _SYS_PROTO_H_ 9*4882a593Smuzhiyun #define _SYS_PROTO_H_ 10*4882a593Smuzhiyun #include <linux/mtd/omap_gpmc.h> 11*4882a593Smuzhiyun #include <asm/omap_common.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun typedef struct { 14*4882a593Smuzhiyun u32 mtype; 15*4882a593Smuzhiyun char *board_string; 16*4882a593Smuzhiyun char *nand_string; 17*4882a593Smuzhiyun } omap3_sysinfo; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct emu_hal_params { 20*4882a593Smuzhiyun u32 num_params; 21*4882a593Smuzhiyun u32 param1; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Board SDRC timing values */ 25*4882a593Smuzhiyun struct board_sdrc_timings { 26*4882a593Smuzhiyun u32 sharing; 27*4882a593Smuzhiyun u32 mcfg; 28*4882a593Smuzhiyun u32 ctrla; 29*4882a593Smuzhiyun u32 ctrlb; 30*4882a593Smuzhiyun u32 rfr_ctrl; 31*4882a593Smuzhiyun u32 mr; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun void prcm_init(void); 35*4882a593Smuzhiyun void per_clocks_enable(void); 36*4882a593Smuzhiyun void ehci_clocks_enable(void); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void memif_init(void); 39*4882a593Smuzhiyun void sdrc_init(void); 40*4882a593Smuzhiyun void do_sdrc_init(u32, u32); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun void get_board_mem_timings(struct board_sdrc_timings *timings); 43*4882a593Smuzhiyun int identify_nand_chip(int *mfr, int *id); 44*4882a593Smuzhiyun void emif4_init(void); 45*4882a593Smuzhiyun void gpmc_init(void); 46*4882a593Smuzhiyun void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, 47*4882a593Smuzhiyun u32 base, u32 size); 48*4882a593Smuzhiyun void set_gpmc_cs0(int flash_type); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun void watchdog_init(void); 51*4882a593Smuzhiyun void set_muxconf_regs(void); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun u32 get_cpu_family(void); 54*4882a593Smuzhiyun u32 get_cpu_rev(void); 55*4882a593Smuzhiyun u32 get_sku_id(void); 56*4882a593Smuzhiyun u32 is_gpmc_muxed(void); 57*4882a593Smuzhiyun u32 get_gpmc0_type(void); 58*4882a593Smuzhiyun u32 get_gpmc0_width(void); 59*4882a593Smuzhiyun u32 is_running_in_sdram(void); 60*4882a593Smuzhiyun u32 is_running_in_sram(void); 61*4882a593Smuzhiyun u32 is_running_in_flash(void); 62*4882a593Smuzhiyun u32 get_device_type(void); 63*4882a593Smuzhiyun void secureworld_exit(void); 64*4882a593Smuzhiyun void try_unlock_memory(void); 65*4882a593Smuzhiyun u32 get_boot_type(void); 66*4882a593Smuzhiyun void invalidate_dcache(u32); 67*4882a593Smuzhiyun u32 wait_on_value(u32, u32, void *, u32); 68*4882a593Smuzhiyun void cancel_out(u32 *num, u32 *den, u32 den_limit); 69*4882a593Smuzhiyun void sdelay(unsigned long); 70*4882a593Smuzhiyun void make_cs1_contiguous(void); 71*4882a593Smuzhiyun int omap_nand_switch_ecc(uint32_t, uint32_t); 72*4882a593Smuzhiyun void power_init_r(void); 73*4882a593Smuzhiyun void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); 74*4882a593Smuzhiyun void omap3_set_aux_cr_secure(u32 acr); 75*4882a593Smuzhiyun u32 warm_reset(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun void save_omap_boot_params(void); 78*4882a593Smuzhiyun #endif 79