1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _OMAP3_REGS_H 8*4882a593Smuzhiyun #define _OMAP3_REGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Register definitions for OMAP3 processors. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * GPMC_CONFIG1 - GPMC_CONFIG7 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Values for GPMC_CONFIG1 - signal control parameters */ 19*4882a593Smuzhiyun #define WRAPBURST (1 << 31) 20*4882a593Smuzhiyun #define READMULTIPLE (1 << 30) 21*4882a593Smuzhiyun #define READTYPE (1 << 29) 22*4882a593Smuzhiyun #define WRITEMULTIPLE (1 << 28) 23*4882a593Smuzhiyun #define WRITETYPE (1 << 27) 24*4882a593Smuzhiyun #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) 25*4882a593Smuzhiyun #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) 26*4882a593Smuzhiyun #define WAITREADMONITORING (1 << 22) 27*4882a593Smuzhiyun #define WAITWRITEMONITORING (1 << 21) 28*4882a593Smuzhiyun #define WAITMONITORINGTIME(x) (((x) & 3) << 18) 29*4882a593Smuzhiyun #define WAITPINSELECT(x) (((x) & 3) << 16) 30*4882a593Smuzhiyun #define DEVICESIZE(x) (((x) & 3) << 12) 31*4882a593Smuzhiyun #define DEVICESIZE_8BIT DEVICESIZE(0) 32*4882a593Smuzhiyun #define DEVICESIZE_16BIT DEVICESIZE(1) 33*4882a593Smuzhiyun #define DEVICETYPE(x) (((x) & 3) << 10) 34*4882a593Smuzhiyun #define DEVICETYPE_NOR DEVICETYPE(0) 35*4882a593Smuzhiyun #define DEVICETYPE_NAND DEVICETYPE(2) 36*4882a593Smuzhiyun #define MUXADDDATA (1 << 9) 37*4882a593Smuzhiyun #define TIMEPARAGRANULARITY (1 << 4) 38*4882a593Smuzhiyun #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Values for GPMC_CONFIG2 - CS timing */ 41*4882a593Smuzhiyun #define CSWROFFTIME(x) (((x) & 0x1f) << 16) 42*4882a593Smuzhiyun #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) 43*4882a593Smuzhiyun #define CSEXTRADELAY (1 << 7) 44*4882a593Smuzhiyun #define CSONTIME(x) (((x) & 0xf) << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Values for GPMC_CONFIG3 - nADV timing */ 47*4882a593Smuzhiyun #define ADVWROFFTIME(x) (((x) & 0x1f) << 16) 48*4882a593Smuzhiyun #define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) 49*4882a593Smuzhiyun #define ADVEXTRADELAY (1 << 7) 50*4882a593Smuzhiyun #define ADVONTIME(x) (((x) & 0xf) << 0) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Values for GPMC_CONFIG4 - nWE and nOE timing */ 53*4882a593Smuzhiyun #define WEOFFTIME(x) (((x) & 0x1f) << 24) 54*4882a593Smuzhiyun #define WEEXTRADELAY (1 << 23) 55*4882a593Smuzhiyun #define WEONTIME(x) (((x) & 0xf) << 16) 56*4882a593Smuzhiyun #define OEOFFTIME(x) (((x) & 0x1f) << 8) 57*4882a593Smuzhiyun #define OEEXTRADELAY (1 << 7) 58*4882a593Smuzhiyun #define OEONTIME(x) (((x) & 0xf) << 0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ 61*4882a593Smuzhiyun #define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) 62*4882a593Smuzhiyun #define RDACCESSTIME(x) (((x) & 0x1f) << 16) 63*4882a593Smuzhiyun #define WRCYCLETIME(x) (((x) & 0x1f) << 8) 64*4882a593Smuzhiyun #define RDCYCLETIME(x) (((x) & 0x1f) << 0) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Values for GPMC_CONFIG6 - misc timings */ 67*4882a593Smuzhiyun #define WRACCESSTIME(x) (((x) & 0x1f) << 24) 68*4882a593Smuzhiyun #define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) 69*4882a593Smuzhiyun #define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) 70*4882a593Smuzhiyun #define CYCLE2CYCLESAMECSEN (1 << 7) 71*4882a593Smuzhiyun #define CYCLE2CYCLEDIFFCSEN (1 << 6) 72*4882a593Smuzhiyun #define BUSTURNAROUND(x) (((x) & 0xf) << 0) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Values for GPMC_CONFIG7 - CS address mapping configuration */ 75*4882a593Smuzhiyun #define MASKADDRESS(x) (((x) & 0xf) << 8) 76*4882a593Smuzhiyun #define CSVALID (1 << 6) 77*4882a593Smuzhiyun #define BASEADDRESS(x) (((x) & 0x3f) << 0) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* _OMAP3_REGS_H */ 80