1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Auther: 3*4882a593Smuzhiyun * Vaibhav Hiremath <hvaibhav@ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 6*4882a593Smuzhiyun * Texas Instruments Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _EMIF_H_ 12*4882a593Smuzhiyun #define _EMIF_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Configuration values 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define EMIF4_TIM1_T_RP (0x3 << 25) 18*4882a593Smuzhiyun #define EMIF4_TIM1_T_RCD (0x3 << 21) 19*4882a593Smuzhiyun #define EMIF4_TIM1_T_WR (0x3 << 17) 20*4882a593Smuzhiyun #define EMIF4_TIM1_T_RAS (0x8 << 12) 21*4882a593Smuzhiyun #define EMIF4_TIM1_T_RC (0xA << 6) 22*4882a593Smuzhiyun #define EMIF4_TIM1_T_RRD (0x2 << 3) 23*4882a593Smuzhiyun #define EMIF4_TIM1_T_WTR (0x2) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define EMIF4_TIM2_T_XP (0x2 << 28) 26*4882a593Smuzhiyun #define EMIF4_TIM2_T_ODT (0x0 << 25) 27*4882a593Smuzhiyun #define EMIF4_TIM2_T_XSNR (0x1C << 16) 28*4882a593Smuzhiyun #define EMIF4_TIM2_T_XSRD (0xC8 << 6) 29*4882a593Smuzhiyun #define EMIF4_TIM2_T_RTP (0x1 << 3) 30*4882a593Smuzhiyun #define EMIF4_TIM2_T_CKE (0x2) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define EMIF4_TIM3_T_RFC (0x25 << 4) 33*4882a593Smuzhiyun #define EMIF4_TIM3_T_RAS_MAX (0x7) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define EMIF4_PWR_IDLE_MODE (0x2 << 30) 36*4882a593Smuzhiyun #define EMIF4_PWR_DPD_DIS (0x0 << 10) 37*4882a593Smuzhiyun #define EMIF4_PWR_DPD_EN (0x1 << 10) 38*4882a593Smuzhiyun #define EMIF4_PWR_LP_MODE (0x0 << 8) 39*4882a593Smuzhiyun #define EMIF4_PWR_PM_TIM (0x0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define EMIF4_INITREF_DIS (0x0 << 31) 42*4882a593Smuzhiyun #define EMIF4_REFRESH_RATE (0x50F) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define EMIF4_CFG_SDRAM_TYP (0x2 << 29) 45*4882a593Smuzhiyun #define EMIF4_CFG_IBANK_POS (0x0 << 27) 46*4882a593Smuzhiyun #define EMIF4_CFG_DDR_TERM (0x0 << 24) 47*4882a593Smuzhiyun #define EMIF4_CFG_DDR2_DDQS (0x1 << 23) 48*4882a593Smuzhiyun #define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) 49*4882a593Smuzhiyun #define EMIF4_CFG_SDR_DRV (0x0 << 18) 50*4882a593Smuzhiyun #define EMIF4_CFG_NARROW_MD (0x0 << 14) 51*4882a593Smuzhiyun #define EMIF4_CFG_CL (0x5 << 10) 52*4882a593Smuzhiyun #define EMIF4_CFG_ROWSIZE (0x0 << 7) 53*4882a593Smuzhiyun #define EMIF4_CFG_IBANK (0x3 << 4) 54*4882a593Smuzhiyun #define EMIF4_CFG_EBANK (0x0 << 3) 55*4882a593Smuzhiyun #define EMIF4_CFG_PGSIZE (0x2) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * EMIF4 PHY Control 1 register configuration 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) 61*4882a593Smuzhiyun #define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) 62*4882a593Smuzhiyun #define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) 63*4882a593Smuzhiyun #define EMIF4_DDR1_PWRDN_EN (0x1 << 6) 64*4882a593Smuzhiyun #define EMIF4_DDR1_READ_LAT (0x6 << 0) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* endif _EMIF_H_ */ 67