1*4882a593Smuzhiyun #ifndef __SDMA_H 2*4882a593Smuzhiyun #define __SDMA_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Copyright (C) 2011 5*4882a593Smuzhiyun * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Functions */ 11*4882a593Smuzhiyun void omap3_dma_init(void); 12*4882a593Smuzhiyun int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, 13*4882a593Smuzhiyun uint32_t sze); 14*4882a593Smuzhiyun int omap3_dma_start_transfer(uint32_t chan); 15*4882a593Smuzhiyun int omap3_dma_wait_for_transfer(uint32_t chan); 16*4882a593Smuzhiyun int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); 17*4882a593Smuzhiyun int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Register settings */ 20*4882a593Smuzhiyun #define CSDP_DATA_TYPE_8BIT 0x0 21*4882a593Smuzhiyun #define CSDP_DATA_TYPE_16BIT 0x1 22*4882a593Smuzhiyun #define CSDP_DATA_TYPE_32BIT 0x2 23*4882a593Smuzhiyun #define CSDP_SRC_BURST_SINGLE (0x0 << 7) 24*4882a593Smuzhiyun #define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) 25*4882a593Smuzhiyun #define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) 26*4882a593Smuzhiyun #define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) 27*4882a593Smuzhiyun #define CSDP_DST_BURST_SINGLE (0x0 << 14) 28*4882a593Smuzhiyun #define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) 29*4882a593Smuzhiyun #define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) 30*4882a593Smuzhiyun #define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) 31*4882a593Smuzhiyun #define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) 32*4882a593Smuzhiyun #define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) 33*4882a593Smuzhiyun #define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) 34*4882a593Smuzhiyun #define CSDP_DST_ENDIAN_BIG (0x1 << 19) 35*4882a593Smuzhiyun #define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) 36*4882a593Smuzhiyun #define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) 37*4882a593Smuzhiyun #define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) 38*4882a593Smuzhiyun #define CSDP_SRC_ENDIAN_BIG (0x1 << 21) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CCR_READ_PRIORITY_LOW (0x0 << 6) 41*4882a593Smuzhiyun #define CCR_READ_PRIORITY_HIGH (0x1 << 6) 42*4882a593Smuzhiyun #define CCR_ENABLE_DISABLED (0x0 << 7) 43*4882a593Smuzhiyun #define CCR_ENABLE_ENABLE (0x1 << 7) 44*4882a593Smuzhiyun #define CCR_SRC_AMODE_CONSTANT (0x0 << 12) 45*4882a593Smuzhiyun #define CCR_SRC_AMODE_POST_INC (0x1 << 12) 46*4882a593Smuzhiyun #define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) 47*4882a593Smuzhiyun #define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) 48*4882a593Smuzhiyun #define CCR_DST_AMODE_CONSTANT (0x0 << 14) 49*4882a593Smuzhiyun #define CCR_DST_AMODE_POST_INC (0x1 << 14) 50*4882a593Smuzhiyun #define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) 51*4882a593Smuzhiyun #define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CCR_RD_ACTIVE_MASK (1 << 9) 54*4882a593Smuzhiyun #define CCR_WR_ACTIVE_MASK (1 << 10) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CSR_TRANS_ERR (1 << 8) 57*4882a593Smuzhiyun #define CSR_SUPERVISOR_ERR (1 << 10) 58*4882a593Smuzhiyun #define CSR_MISALIGNED_ADRS_ERR (1 << 11) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* others */ 61*4882a593Smuzhiyun #define CHAN_NR_MIN 0 62*4882a593Smuzhiyun #define CHAN_NR_MAX 31 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __SDMA_H */ 65