1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * am35x_def.h - TI's AM35x specific definitions. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Based on arch/arm/include/asm/arch-omap3/cpu.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (c) 2010 Texas Instruments Incorporated 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _AM35X_DEF_H_ 14*4882a593Smuzhiyun #define _AM35X_DEF_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 17*4882a593Smuzhiyun #include <asm/types.h> 18*4882a593Smuzhiyun #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef __KERNEL_STRICT_NAMES 21*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* LVL_INTR_CLEAR bits */ 24*4882a593Smuzhiyun #define USBOTGSS_INT_CLR (1 << 4) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* IP_SW_RESET bits */ 27*4882a593Smuzhiyun #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ 28*4882a593Smuzhiyun #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* DEVCONF2 bits */ 31*4882a593Smuzhiyun #define CONF2_PHY_GPIOMODE (1 << 23) 32*4882a593Smuzhiyun #define CONF2_OTGMODE (3 << 14) 33*4882a593Smuzhiyun #define CONF2_NO_OVERRIDE (0 << 14) 34*4882a593Smuzhiyun #define CONF2_FORCE_HOST (1 << 14) 35*4882a593Smuzhiyun #define CONF2_FORCE_DEVICE (2 << 14) 36*4882a593Smuzhiyun #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) 37*4882a593Smuzhiyun #define CONF2_SESENDEN (1 << 13) 38*4882a593Smuzhiyun #define CONF2_VBDTCTEN (1 << 12) 39*4882a593Smuzhiyun #define CONF2_REFFREQ_24MHZ (2 << 8) 40*4882a593Smuzhiyun #define CONF2_REFFREQ_26MHZ (7 << 8) 41*4882a593Smuzhiyun #define CONF2_REFFREQ_13MHZ (6 << 8) 42*4882a593Smuzhiyun #define CONF2_REFFREQ (0xf << 8) 43*4882a593Smuzhiyun #define CONF2_PHYCLKGD (1 << 7) 44*4882a593Smuzhiyun #define CONF2_VBUSSENSE (1 << 6) 45*4882a593Smuzhiyun #define CONF2_PHY_PLLON (1 << 5) 46*4882a593Smuzhiyun #define CONF2_RESET (1 << 4) 47*4882a593Smuzhiyun #define CONF2_PHYPWRDN (1 << 3) 48*4882a593Smuzhiyun #define CONF2_OTGPWRDN (1 << 2) 49*4882a593Smuzhiyun #define CONF2_DATPOL (1 << 1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* General register mappings of system control module */ 52*4882a593Smuzhiyun #define AM35X_SCM_GEN_BASE 0x48002270 53*4882a593Smuzhiyun struct am35x_scm_general { 54*4882a593Smuzhiyun u32 res1[0xC4]; /* 0x000 - 0x30C */ 55*4882a593Smuzhiyun u32 devconf2; /* 0x310 */ 56*4882a593Smuzhiyun u32 devconf3; /* 0x314 */ 57*4882a593Smuzhiyun u32 res2[0x2]; /* 0x318 - 0x31C */ 58*4882a593Smuzhiyun u32 cba_priority; /* 0x320 */ 59*4882a593Smuzhiyun u32 lvl_intr_clr; /* 0x324 */ 60*4882a593Smuzhiyun u32 ip_sw_reset; /* 0x328 */ 61*4882a593Smuzhiyun u32 ipss_clk_ctrl; /* 0x32C */ 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /*__ASSEMBLY__ */ 68*4882a593Smuzhiyun #endif /* __KERNEL_STRICT_NAMES */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _AM35X_DEF_H_ */ 71