1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX23/i.MX28 specific functions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MXS_SYS_PROTO_H__ 11*4882a593Smuzhiyun #define __MXS_SYS_PROTO_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/mach-imx/sys_proto.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #if defined(CONFIG_MX23) 20*4882a593Smuzhiyun #include <asm/arch/iomux-mx23.h> 21*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 22*4882a593Smuzhiyun #include <asm/arch/iomux-mx28.h> 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, 26*4882a593Smuzhiyun const iomux_cfg_t *iomux_setup, 27*4882a593Smuzhiyun const unsigned int iomux_size); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct mxs_pair { 33*4882a593Smuzhiyun uint8_t boot_pads; 34*4882a593Smuzhiyun uint8_t boot_mask; 35*4882a593Smuzhiyun const char *mode; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun static const struct mxs_pair mxs_boot_modes[] = { 39*4882a593Smuzhiyun #if defined(CONFIG_MX23) 40*4882a593Smuzhiyun { 0x00, 0x0f, "USB" }, 41*4882a593Smuzhiyun { 0x01, 0x1f, "I2C, master" }, 42*4882a593Smuzhiyun { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, 43*4882a593Smuzhiyun { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, 44*4882a593Smuzhiyun { 0x04, 0x1f, "NAND" }, 45*4882a593Smuzhiyun { 0x06, 0x1f, "JTAG" }, 46*4882a593Smuzhiyun { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, 47*4882a593Smuzhiyun { 0x09, 0x1f, "SSP SD/MMC #0" }, 48*4882a593Smuzhiyun { 0x0a, 0x1f, "SSP SD/MMC #1" }, 49*4882a593Smuzhiyun { 0x00, 0x00, "Reserved/Unknown/Wrong" }, 50*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 51*4882a593Smuzhiyun { 0x00, 0x0f, "USB #0" }, 52*4882a593Smuzhiyun { 0x01, 0x1f, "I2C #0, master, 3V3" }, 53*4882a593Smuzhiyun { 0x11, 0x1f, "I2C #0, master, 1V8" }, 54*4882a593Smuzhiyun { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, 55*4882a593Smuzhiyun { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, 56*4882a593Smuzhiyun { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, 57*4882a593Smuzhiyun { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, 58*4882a593Smuzhiyun { 0x04, 0x1f, "NAND, 3V3" }, 59*4882a593Smuzhiyun { 0x14, 0x1f, "NAND, 1V8" }, 60*4882a593Smuzhiyun { 0x06, 0x1f, "JTAG" }, 61*4882a593Smuzhiyun { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, 62*4882a593Smuzhiyun { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, 63*4882a593Smuzhiyun { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, 64*4882a593Smuzhiyun { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, 65*4882a593Smuzhiyun { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, 66*4882a593Smuzhiyun { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, 67*4882a593Smuzhiyun { 0x00, 0x00, "Reserved/Unknown/Wrong" }, 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define MXS_BM_USB 0x00 72*4882a593Smuzhiyun #define MXS_BM_I2C_MASTER_3V3 0x01 73*4882a593Smuzhiyun #define MXS_BM_I2C_MASTER_1V8 0x11 74*4882a593Smuzhiyun #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 75*4882a593Smuzhiyun #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 76*4882a593Smuzhiyun #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 77*4882a593Smuzhiyun #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 78*4882a593Smuzhiyun #define MXS_BM_NAND_3V3 0x04 79*4882a593Smuzhiyun #define MXS_BM_NAND_1V8 0x14 80*4882a593Smuzhiyun #define MXS_BM_JTAG 0x06 81*4882a593Smuzhiyun #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 82*4882a593Smuzhiyun #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 83*4882a593Smuzhiyun #define MXS_BM_SDMMC0_3V3 0x09 84*4882a593Smuzhiyun #define MXS_BM_SDMMC0_1V8 0x19 85*4882a593Smuzhiyun #define MXS_BM_SDMMC1_3V3 0x0a 86*4882a593Smuzhiyun #define MXS_BM_SDMMC1_1V8 0x1a 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct mxs_spl_data { 89*4882a593Smuzhiyun uint8_t boot_mode_idx; 90*4882a593Smuzhiyun uint32_t mem_dram_size; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun int mxs_dram_init(void); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif /* __SYS_PROTO_H__ */ 96