1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX28 TIMROT Register Definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on code from LTIB: 7*4882a593Smuzhiyun * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __MX28_REGS_TIMROT_H__ 13*4882a593Smuzhiyun #define __MX28_REGS_TIMROT_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/mach-imx/regs-common.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 18*4882a593Smuzhiyun struct mxs_timrot_regs { 19*4882a593Smuzhiyun mxs_reg_32(hw_timrot_rotctrl) 20*4882a593Smuzhiyun mxs_reg_32(hw_timrot_rotcount) 21*4882a593Smuzhiyun #if defined(CONFIG_MX23) 22*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl0) 23*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timcount0) 24*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl1) 25*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timcount1) 26*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl2) 27*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timcount2) 28*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl3) 29*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timcount3) 30*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 31*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl0) 32*4882a593Smuzhiyun mxs_reg_32(hw_timrot_running_count0) 33*4882a593Smuzhiyun mxs_reg_32(hw_timrot_fixed_count0) 34*4882a593Smuzhiyun mxs_reg_32(hw_timrot_match_count0) 35*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl1) 36*4882a593Smuzhiyun mxs_reg_32(hw_timrot_running_count1) 37*4882a593Smuzhiyun mxs_reg_32(hw_timrot_fixed_count1) 38*4882a593Smuzhiyun mxs_reg_32(hw_timrot_match_count1) 39*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl2) 40*4882a593Smuzhiyun mxs_reg_32(hw_timrot_running_count2) 41*4882a593Smuzhiyun mxs_reg_32(hw_timrot_fixed_count2) 42*4882a593Smuzhiyun mxs_reg_32(hw_timrot_match_count2) 43*4882a593Smuzhiyun mxs_reg_32(hw_timrot_timctrl3) 44*4882a593Smuzhiyun mxs_reg_32(hw_timrot_running_count3) 45*4882a593Smuzhiyun mxs_reg_32(hw_timrot_fixed_count3) 46*4882a593Smuzhiyun mxs_reg_32(hw_timrot_match_count3) 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun mxs_reg_32(hw_timrot_version) 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SFTRST (1 << 31) 53*4882a593Smuzhiyun #define TIMROT_ROTCTRL_CLKGATE (1 << 30) 54*4882a593Smuzhiyun #define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) 55*4882a593Smuzhiyun #define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) 56*4882a593Smuzhiyun #define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) 57*4882a593Smuzhiyun #define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) 58*4882a593Smuzhiyun #define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) 59*4882a593Smuzhiyun #define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) 60*4882a593Smuzhiyun #define TIMROT_ROTCTRL_STATE_OFFSET 22 61*4882a593Smuzhiyun #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) 62*4882a593Smuzhiyun #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 63*4882a593Smuzhiyun #define TIMROT_ROTCTRL_RELATIVE (1 << 12) 64*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) 65*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 66*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) 67*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) 68*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) 69*4882a593Smuzhiyun #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) 70*4882a593Smuzhiyun #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) 71*4882a593Smuzhiyun #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) 72*4882a593Smuzhiyun #if defined(CONFIG_MX23) 73*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) 74*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 75*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 78*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) 79*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) 80*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) 81*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) 82*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) 83*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) 84*4882a593Smuzhiyun #if defined(CONFIG_MX23) 85*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) 86*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) 87*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 88*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) 89*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) 90*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) 91*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) 92*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun #if defined(CONFIG_MX23) 95*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 96*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 97*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf 98*4882a593Smuzhiyun #endif 99*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 100*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 101*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 102*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 103*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 104*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 105*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 106*4882a593Smuzhiyun #if defined(CONFIG_MX23) 107*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 108*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 109*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 110*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 111*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 112*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 113*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 114*4882a593Smuzhiyun #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff 118*4882a593Smuzhiyun #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_IRQ (1 << 15) 121*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) 122*4882a593Smuzhiyun #if defined(CONFIG_MX28) 123*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) 124*4882a593Smuzhiyun #endif 125*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_POLARITY (1 << 8) 126*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_UPDATE (1 << 7) 127*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_RELOAD (1 << 6) 128*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) 129*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 130*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) 131*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) 132*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) 133*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) 134*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_MASK 0xf 135*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_OFFSET 0 136*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 137*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 138*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 139*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 140*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 141*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 142*4882a593Smuzhiyun #if defined(CONFIG_MX23) 143*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 144*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 145*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 146*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 147*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa 148*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb 149*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc 150*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 151*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 152*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 153*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 154*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 155*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa 156*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb 157*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc 158*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd 159*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe 160*4882a593Smuzhiyun #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf 161*4882a593Smuzhiyun #endif 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #if defined(CONFIG_MX23) 164*4882a593Smuzhiyun #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) 165*4882a593Smuzhiyun #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 166*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 167*4882a593Smuzhiyun #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff 168*4882a593Smuzhiyun #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 169*4882a593Smuzhiyun #endif 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #if defined(CONFIG_MX23) 172*4882a593Smuzhiyun #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff 173*4882a593Smuzhiyun #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 174*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 175*4882a593Smuzhiyun #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff 176*4882a593Smuzhiyun #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #if defined(CONFIG_MX28) 180*4882a593Smuzhiyun #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff 181*4882a593Smuzhiyun #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 182*4882a593Smuzhiyun #endif 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) 185*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 186*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) 187*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) 188*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) 189*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) 190*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) 191*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) 192*4882a593Smuzhiyun #if defined(CONFIG_MX23) 193*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) 194*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) 195*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) 196*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) 197*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) 198*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) 199*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) 200*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 201*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) 202*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) 203*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) 204*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) 205*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) 206*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) 207*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) 208*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) 209*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) 210*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) 211*4882a593Smuzhiyun #endif 212*4882a593Smuzhiyun #if defined(CONFIG_MX23) 213*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_IRQ (1 << 15) 214*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) 215*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) 216*4882a593Smuzhiyun #endif 217*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) 218*4882a593Smuzhiyun #if defined(CONFIG_MX23) 219*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) 220*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 221*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) 222*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) 223*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_UPDATE (1 << 7) 224*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_RELOAD (1 << 6) 225*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) 226*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 227*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) 228*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) 229*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) 230*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) 231*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_MASK 0xf 232*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_OFFSET 0 233*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 234*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 235*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 236*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 237*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 238*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 239*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 240*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 241*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 242*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 243*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa 244*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb 245*4882a593Smuzhiyun #define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc 246*4882a593Smuzhiyun #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) 247*4882a593Smuzhiyun #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 248*4882a593Smuzhiyun #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff 249*4882a593Smuzhiyun #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 250*4882a593Smuzhiyun #endif 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define TIMROT_VERSION_MAJOR_MASK (0xff << 24) 253*4882a593Smuzhiyun #define TIMROT_VERSION_MAJOR_OFFSET 24 254*4882a593Smuzhiyun #define TIMROT_VERSION_MINOR_MASK (0xff << 16) 255*4882a593Smuzhiyun #define TIMROT_VERSION_MINOR_OFFSET 16 256*4882a593Smuzhiyun #define TIMROT_VERSION_STEP_MASK 0xffff 257*4882a593Smuzhiyun #define TIMROT_VERSION_STEP_OFFSET 0 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #endif /* __MX28_REGS_TIMROT_H__ */ 260