1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX28 RTC Register Definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MX28_REGS_RTC_H__ 11*4882a593Smuzhiyun #define __MX28_REGS_RTC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/mach-imx/regs-common.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 16*4882a593Smuzhiyun struct mxs_rtc_regs { 17*4882a593Smuzhiyun mxs_reg_32(hw_rtc_ctrl) 18*4882a593Smuzhiyun mxs_reg_32(hw_rtc_stat) 19*4882a593Smuzhiyun mxs_reg_32(hw_rtc_milliseconds) 20*4882a593Smuzhiyun mxs_reg_32(hw_rtc_seconds) 21*4882a593Smuzhiyun mxs_reg_32(hw_rtc_rtc_alarm) 22*4882a593Smuzhiyun mxs_reg_32(hw_rtc_watchdog) 23*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent0) 24*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent1) 25*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent2) 26*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent3) 27*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent4) 28*4882a593Smuzhiyun mxs_reg_32(hw_rtc_persistent5) 29*4882a593Smuzhiyun mxs_reg_32(hw_rtc_debug) 30*4882a593Smuzhiyun mxs_reg_32(hw_rtc_version) 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define RTC_CTRL_SFTRST (1 << 31) 35*4882a593Smuzhiyun #define RTC_CTRL_CLKGATE (1 << 30) 36*4882a593Smuzhiyun #define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) 37*4882a593Smuzhiyun #define RTC_CTRL_FORCE_UPDATE (1 << 5) 38*4882a593Smuzhiyun #define RTC_CTRL_WATCHDOGEN (1 << 4) 39*4882a593Smuzhiyun #define RTC_CTRL_ONEMSEC_IRQ (1 << 3) 40*4882a593Smuzhiyun #define RTC_CTRL_ALARM_IRQ (1 << 2) 41*4882a593Smuzhiyun #define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) 42*4882a593Smuzhiyun #define RTC_CTRL_ALARM_IRQ_EN (1 << 0) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define RTC_STAT_RTC_PRESENT (1 << 31) 45*4882a593Smuzhiyun #define RTC_STAT_ALARM_PRESENT (1 << 30) 46*4882a593Smuzhiyun #define RTC_STAT_WATCHDOG_PRESENT (1 << 29) 47*4882a593Smuzhiyun #define RTC_STAT_XTAL32000_PRESENT (1 << 28) 48*4882a593Smuzhiyun #define RTC_STAT_XTAL32768_PRESENT (1 << 27) 49*4882a593Smuzhiyun #define RTC_STAT_STALE_REGS_MASK (0xff << 16) 50*4882a593Smuzhiyun #define RTC_STAT_STALE_REGS_OFFSET 16 51*4882a593Smuzhiyun #define RTC_STAT_NEW_REGS_MASK (0xff << 8) 52*4882a593Smuzhiyun #define RTC_STAT_NEW_REGS_OFFSET 8 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define RTC_MILLISECONDS_COUNT_MASK 0xffffffff 55*4882a593Smuzhiyun #define RTC_MILLISECONDS_COUNT_OFFSET 0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define RTC_SECONDS_COUNT_MASK 0xffffffff 58*4882a593Smuzhiyun #define RTC_SECONDS_COUNT_OFFSET 0 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define RTC_ALARM_VALUE_MASK 0xffffffff 61*4882a593Smuzhiyun #define RTC_ALARM_VALUE_OFFSET 0 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define RTC_WATCHDOG_COUNT_MASK 0xffffffff 64*4882a593Smuzhiyun #define RTC_WATCHDOG_COUNT_OFFSET 0 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) 67*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 68*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) 69*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) 70*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) 71*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) 72*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) 73*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) 74*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) 75*4882a593Smuzhiyun #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) 76*4882a593Smuzhiyun #define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) 77*4882a593Smuzhiyun #define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) 78*4882a593Smuzhiyun #define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) 79*4882a593Smuzhiyun #define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) 80*4882a593Smuzhiyun #define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) 81*4882a593Smuzhiyun #define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) 82*4882a593Smuzhiyun #define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 83*4882a593Smuzhiyun #define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) 84*4882a593Smuzhiyun #define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) 85*4882a593Smuzhiyun #define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) 86*4882a593Smuzhiyun #define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) 87*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) 88*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 89*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) 90*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) 91*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) 92*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) 93*4882a593Smuzhiyun #define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) 94*4882a593Smuzhiyun #define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) 95*4882a593Smuzhiyun #define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) 96*4882a593Smuzhiyun #define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) 97*4882a593Smuzhiyun #define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) 98*4882a593Smuzhiyun #define RTC_PERSISTENT0_LCK_SECS (1 << 3) 99*4882a593Smuzhiyun #define RTC_PERSISTENT0_ALARM_EN (1 << 2) 100*4882a593Smuzhiyun #define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) 101*4882a593Smuzhiyun #define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff 104*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_OFFSET 0 105*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 106*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 107*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 108*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 109*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 110*4882a593Smuzhiyun #define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff 113*4882a593Smuzhiyun #define RTC_PERSISTENT2_GENERAL_OFFSET 0 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff 116*4882a593Smuzhiyun #define RTC_PERSISTENT3_GENERAL_OFFSET 0 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff 119*4882a593Smuzhiyun #define RTC_PERSISTENT4_GENERAL_OFFSET 0 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff 122*4882a593Smuzhiyun #define RTC_PERSISTENT5_GENERAL_OFFSET 0 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) 125*4882a593Smuzhiyun #define RTC_DEBUG_WATCHDOG_RESET (1 << 0) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define RTC_VERSION_MAJOR_MASK (0xff << 24) 128*4882a593Smuzhiyun #define RTC_VERSION_MAJOR_OFFSET 24 129*4882a593Smuzhiyun #define RTC_VERSION_MINOR_MASK (0xff << 16) 130*4882a593Smuzhiyun #define RTC_VERSION_MINOR_OFFSET 16 131*4882a593Smuzhiyun #define RTC_VERSION_STEP_MASK 0xffff 132*4882a593Smuzhiyun #define RTC_VERSION_STEP_OFFSET 0 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* __MX28_REGS_RTC_H__ */ 135