1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX23/i.MX28 Peripheral Base Addresses 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on code from LTIB: 8*4882a593Smuzhiyun * Copyright (C) 2008 Embedded Alley Solutions Inc. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __MXS_REGS_BASE_H__ 16*4882a593Smuzhiyun #define __MXS_REGS_BASE_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Register base addresses for i.MX23 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #if defined(CONFIG_MX23) 22*4882a593Smuzhiyun #define MXS_ICOLL_BASE 0x80000000 23*4882a593Smuzhiyun #define MXS_APBH_BASE 0x80004000 24*4882a593Smuzhiyun #define MXS_ECC8_BASE 0x80008000 25*4882a593Smuzhiyun #define MXS_BCH_BASE 0x8000A000 26*4882a593Smuzhiyun #define MXS_GPMI_BASE 0x8000C000 27*4882a593Smuzhiyun #define MXS_SSP0_BASE 0x80010000 28*4882a593Smuzhiyun #define MXS_SSP1_BASE 0x80034000 29*4882a593Smuzhiyun #define MXS_ETM_BASE 0x80014000 30*4882a593Smuzhiyun #define MXS_PINCTRL_BASE 0x80018000 31*4882a593Smuzhiyun #define MXS_DIGCTL_BASE 0x8001C000 32*4882a593Smuzhiyun #define MXS_EMI_BASE 0x80020000 33*4882a593Smuzhiyun #define MXS_APBX_BASE 0x80024000 34*4882a593Smuzhiyun #define MXS_DCP_BASE 0x80028000 35*4882a593Smuzhiyun #define MXS_PXP_BASE 0x8002A000 36*4882a593Smuzhiyun #define MXS_OCOTP_BASE 0x8002C000 37*4882a593Smuzhiyun #define MXS_AXI_BASE 0x8002E000 38*4882a593Smuzhiyun #define MXS_LCDIF_BASE 0x80030000 39*4882a593Smuzhiyun #define MXS_SSP1_BASE 0x80034000 40*4882a593Smuzhiyun #define MXS_TVENC_BASE 0x80038000 41*4882a593Smuzhiyun #define MXS_CLKCTRL_BASE 0x80040000 42*4882a593Smuzhiyun #define MXS_SAIF0_BASE 0x80042000 43*4882a593Smuzhiyun #define MXS_POWER_BASE 0x80044000 44*4882a593Smuzhiyun #define MXS_SAIF1_BASE 0x80046000 45*4882a593Smuzhiyun #define MXS_AUDIOOUT_BASE 0x80048000 46*4882a593Smuzhiyun #define MXS_AUDIOIN_BASE 0x8004C000 47*4882a593Smuzhiyun #define MXS_LRADC_BASE 0x80050000 48*4882a593Smuzhiyun #define MXS_SPDIF_BASE 0x80054000 49*4882a593Smuzhiyun #define MXS_I2C0_BASE 0x80058000 50*4882a593Smuzhiyun #define MXS_RTC_BASE 0x8005C000 51*4882a593Smuzhiyun #define MXS_PWM_BASE 0x80064000 52*4882a593Smuzhiyun #define MXS_TIMROT_BASE 0x80068000 53*4882a593Smuzhiyun #define MXS_UARTAPP0_BASE 0x8006C000 54*4882a593Smuzhiyun #define MXS_UARTAPP1_BASE 0x8006E000 55*4882a593Smuzhiyun #define MXS_UARTDBG_BASE 0x80070000 56*4882a593Smuzhiyun #define MXS_USBPHY0_BASE 0x8007C000 57*4882a593Smuzhiyun #define MXS_USBCTRL0_BASE 0x80080000 58*4882a593Smuzhiyun #define MXS_DRAM_BASE 0x800E0000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Register base addresses for i.MX28 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 64*4882a593Smuzhiyun #define MXS_ICOL_BASE 0x80000000 65*4882a593Smuzhiyun #define MXS_HSADC_BASE 0x80002000 66*4882a593Smuzhiyun #define MXS_APBH_BASE 0x80004000 67*4882a593Smuzhiyun #define MXS_PERFMON_BASE 0x80006000 68*4882a593Smuzhiyun #define MXS_BCH_BASE 0x8000A000 69*4882a593Smuzhiyun #define MXS_GPMI_BASE 0x8000C000 70*4882a593Smuzhiyun #define MXS_SSP0_BASE 0x80010000 71*4882a593Smuzhiyun #define MXS_SSP1_BASE 0x80012000 72*4882a593Smuzhiyun #define MXS_SSP2_BASE 0x80014000 73*4882a593Smuzhiyun #define MXS_SSP3_BASE 0x80016000 74*4882a593Smuzhiyun #define MXS_PINCTRL_BASE 0x80018000 75*4882a593Smuzhiyun #define MXS_DIGCTL_BASE 0x8001C000 76*4882a593Smuzhiyun #define MXS_ETM_BASE 0x80022000 77*4882a593Smuzhiyun #define MXS_APBX_BASE 0x80024000 78*4882a593Smuzhiyun #define MXS_DCP_BASE 0x80028000 79*4882a593Smuzhiyun #define MXS_PXP_BASE 0x8002A000 80*4882a593Smuzhiyun #define MXS_OCOTP_BASE 0x8002C000 81*4882a593Smuzhiyun #define MXS_AXI_AHB0_BASE 0x8002E000 82*4882a593Smuzhiyun #define MXS_LCDIF_BASE 0x80030000 83*4882a593Smuzhiyun #define MXS_CAN0_BASE 0x80032000 84*4882a593Smuzhiyun #define MXS_CAN1_BASE 0x80034000 85*4882a593Smuzhiyun #define MXS_SIMDBG_BASE 0x8003C000 86*4882a593Smuzhiyun #define MXS_SIMGPMISEL_BASE 0x8003C200 87*4882a593Smuzhiyun #define MXS_SIMSSPSEL_BASE 0x8003C300 88*4882a593Smuzhiyun #define MXS_SIMMEMSEL_BASE 0x8003C400 89*4882a593Smuzhiyun #define MXS_GPIOMON_BASE 0x8003C500 90*4882a593Smuzhiyun #define MXS_SIMENET_BASE 0x8003C700 91*4882a593Smuzhiyun #define MXS_ARMJTAG_BASE 0x8003C800 92*4882a593Smuzhiyun #define MXS_CLKCTRL_BASE 0x80040000 93*4882a593Smuzhiyun #define MXS_SAIF0_BASE 0x80042000 94*4882a593Smuzhiyun #define MXS_POWER_BASE 0x80044000 95*4882a593Smuzhiyun #define MXS_SAIF1_BASE 0x80046000 96*4882a593Smuzhiyun #define MXS_LRADC_BASE 0x80050000 97*4882a593Smuzhiyun #define MXS_SPDIF_BASE 0x80054000 98*4882a593Smuzhiyun #define MXS_RTC_BASE 0x80056000 99*4882a593Smuzhiyun #define MXS_I2C0_BASE 0x80058000 100*4882a593Smuzhiyun #define MXS_I2C1_BASE 0x8005A000 101*4882a593Smuzhiyun #define MXS_PWM_BASE 0x80064000 102*4882a593Smuzhiyun #define MXS_TIMROT_BASE 0x80068000 103*4882a593Smuzhiyun #define MXS_UARTAPP0_BASE 0x8006A000 104*4882a593Smuzhiyun #define MXS_UARTAPP1_BASE 0x8006C000 105*4882a593Smuzhiyun #define MXS_UARTAPP2_BASE 0x8006E000 106*4882a593Smuzhiyun #define MXS_UARTAPP3_BASE 0x80070000 107*4882a593Smuzhiyun #define MXS_UARTAPP4_BASE 0x80072000 108*4882a593Smuzhiyun #define MXS_UARTDBG_BASE 0x80074000 109*4882a593Smuzhiyun #define MXS_USBPHY0_BASE 0x8007C000 110*4882a593Smuzhiyun #define MXS_USBPHY1_BASE 0x8007E000 111*4882a593Smuzhiyun #define MXS_USBCTRL0_BASE 0x80080000 112*4882a593Smuzhiyun #define MXS_USBCTRL1_BASE 0x80090000 113*4882a593Smuzhiyun #define MXS_DFLPT_BASE 0x800C0000 114*4882a593Smuzhiyun #define MXS_DRAM_BASE 0x800E0000 115*4882a593Smuzhiyun #define MXS_ENET0_BASE 0x800F0000 116*4882a593Smuzhiyun #define MXS_ENET1_BASE 0x800F4000 117*4882a593Smuzhiyun #else 118*4882a593Smuzhiyun #error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 119*4882a593Smuzhiyun #endif 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif /* __MXS_REGS_BASE_H__ */ 122