xref: /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mxs/clock.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Freescale i.MX23/i.MX28 Clock
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5*4882a593Smuzhiyun  * on behalf of DENX Software Engineering GmbH
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __CLOCK_H__
11*4882a593Smuzhiyun #define __CLOCK_H__
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun enum mxc_clock {
14*4882a593Smuzhiyun 	MXC_ARM_CLK = 0,
15*4882a593Smuzhiyun 	MXC_AHB_CLK,
16*4882a593Smuzhiyun 	MXC_IPG_CLK,
17*4882a593Smuzhiyun 	MXC_EMI_CLK,
18*4882a593Smuzhiyun 	MXC_GPMI_CLK,
19*4882a593Smuzhiyun 	MXC_IO0_CLK,
20*4882a593Smuzhiyun 	MXC_IO1_CLK,
21*4882a593Smuzhiyun 	MXC_XTAL_CLK,
22*4882a593Smuzhiyun 	MXC_SSP0_CLK,
23*4882a593Smuzhiyun #ifdef CONFIG_MX28
24*4882a593Smuzhiyun 	MXC_SSP1_CLK,
25*4882a593Smuzhiyun 	MXC_SSP2_CLK,
26*4882a593Smuzhiyun 	MXC_SSP3_CLK,
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun enum mxs_ioclock {
31*4882a593Smuzhiyun 	MXC_IOCLK0 = 0,
32*4882a593Smuzhiyun 	MXC_IOCLK1,
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun enum mxs_sspclock {
36*4882a593Smuzhiyun 	MXC_SSPCLK0 = 0,
37*4882a593Smuzhiyun #ifdef CONFIG_MX28
38*4882a593Smuzhiyun 	MXC_SSPCLK1,
39*4882a593Smuzhiyun 	MXC_SSPCLK2,
40*4882a593Smuzhiyun 	MXC_SSPCLK3,
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun uint32_t mxc_get_clock(enum mxc_clock clk);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
47*4882a593Smuzhiyun void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
48*4882a593Smuzhiyun void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
49*4882a593Smuzhiyun void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* Compatibility with the FEC Ethernet driver */
52*4882a593Smuzhiyun #define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #endif	/* __CLOCK_H__ */
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