1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Based on Linux i.MX iomux-v3.h file: 3*4882a593Smuzhiyun * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, 4*4882a593Smuzhiyun * <armlinux@phytec.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __MACH_IOMUX_H__ 12*4882a593Smuzhiyun #define __MACH_IOMUX_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * build IOMUX_PAD structure 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * This iomux scheme is based around pads, which are the physical balls 18*4882a593Smuzhiyun * on the processor. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls 21*4882a593Smuzhiyun * things like driving strength and pullup/pulldown. 22*4882a593Smuzhiyun * - Each pad can have but not necessarily does have an output routing register 23*4882a593Smuzhiyun * (IOMUXC_SW_MUX_CTL_PAD_x). 24*4882a593Smuzhiyun * - Each pad can have but not necessarily does have an input routing register 25*4882a593Smuzhiyun * (IOMUXC_x_SELECT_INPUT) 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * The three register sets do not have a fixed offset to each other, 28*4882a593Smuzhiyun * hence we order this table by pad control registers (which all pads 29*4882a593Smuzhiyun * have) and put the optional i/o routing registers into additional 30*4882a593Smuzhiyun * fields. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> 33*4882a593Smuzhiyun * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * IOMUX/PAD Bit field definitions 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * MUX_CTRL_OFS: 0..15 (16) 38*4882a593Smuzhiyun * SEL_INPUT_OFS: 16..31 (16) 39*4882a593Smuzhiyun * MUX_MODE: 32..37 (6) 40*4882a593Smuzhiyun * SEL_INP: 38..41 (4) 41*4882a593Smuzhiyun * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) 42*4882a593Smuzhiyun * reserved: 61-63 (3) 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun typedef u64 iomux_cfg_t; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MUX_CTRL_OFS_SHIFT 0 48*4882a593Smuzhiyun #define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) 49*4882a593Smuzhiyun #define MUX_SEL_INPUT_OFS_SHIFT 16 50*4882a593Smuzhiyun #define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ 51*4882a593Smuzhiyun MUX_SEL_INPUT_OFS_SHIFT) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MUX_MODE_SHIFT 32 54*4882a593Smuzhiyun #define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) 55*4882a593Smuzhiyun #define MUX_SEL_INPUT_SHIFT 38 56*4882a593Smuzhiyun #define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) 57*4882a593Smuzhiyun #define MUX_PAD_CTRL_SHIFT 42 58*4882a593Smuzhiyun #define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ 63*4882a593Smuzhiyun sel_input, pad_ctrl) \ 64*4882a593Smuzhiyun (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ 65*4882a593Smuzhiyun ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ 66*4882a593Smuzhiyun ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ 67*4882a593Smuzhiyun ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ 68*4882a593Smuzhiyun ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ 71*4882a593Smuzhiyun MUX_PAD_CTRL(pad)) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define IOMUX_CONFIG_MPORTS 0x20 75*4882a593Smuzhiyun #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ 76*4882a593Smuzhiyun MUX_MODE_SHIFT) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Bit definition below needs to be fixed acccording to ulp rm */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define NO_PAD_CTRL (1 << 18) 81*4882a593Smuzhiyun #define PAD_CTL_OBE_ENABLE (1 << 17) 82*4882a593Smuzhiyun #define PAD_CTL_IBE_ENABLE (1 << 16) 83*4882a593Smuzhiyun #define PAD_CTL_DSE (1 << 6) 84*4882a593Smuzhiyun #define PAD_CTL_ODE (1 << 5) 85*4882a593Smuzhiyun #define PAD_CTL_SRE_FAST (0 << 2) 86*4882a593Smuzhiyun #define PAD_CTL_SRE_SLOW (1 << 2) 87*4882a593Smuzhiyun #define PAD_CTL_PUE (1 << 1) 88*4882a593Smuzhiyun #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) 89*4882a593Smuzhiyun #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); 93*4882a593Smuzhiyun void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, 94*4882a593Smuzhiyun unsigned count); 95*4882a593Smuzhiyun #endif /* __MACH_IOMUX_H__*/ 96