1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_CLOCK_H 8*4882a593Smuzhiyun #define _ASM_ARCH_CLOCK_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/arch/pcc.h> 12*4882a593Smuzhiyun #include <asm/arch/scg.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Mainly for compatible to imx common code. */ 15*4882a593Smuzhiyun enum mxc_clock { 16*4882a593Smuzhiyun MXC_ARM_CLK = 0, 17*4882a593Smuzhiyun MXC_AHB_CLK, 18*4882a593Smuzhiyun MXC_IPG_CLK, 19*4882a593Smuzhiyun MXC_UART_CLK, 20*4882a593Smuzhiyun MXC_CSPI_CLK, 21*4882a593Smuzhiyun MXC_AXI_CLK, 22*4882a593Smuzhiyun MXC_DDR_CLK, 23*4882a593Smuzhiyun MXC_ESDHC_CLK, 24*4882a593Smuzhiyun MXC_ESDHC2_CLK, 25*4882a593Smuzhiyun MXC_I2C_CLK, 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun u32 mxc_get_clock(enum mxc_clock clk); 29*4882a593Smuzhiyun u32 get_lpuart_clk(void); 30*4882a593Smuzhiyun #ifdef CONFIG_SYS_LPI2C_IMX 31*4882a593Smuzhiyun int enable_i2c_clk(unsigned char enable, unsigned i2c_num); 32*4882a593Smuzhiyun u32 imx_get_i2cclk(unsigned i2c_num); 33*4882a593Smuzhiyun #endif 34*4882a593Smuzhiyun #ifdef CONFIG_MXC_OCOTP 35*4882a593Smuzhiyun void enable_ocotp_clk(unsigned char enable); 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun #ifdef CONFIG_USB_EHCI_HCD 38*4882a593Smuzhiyun void enable_usboh3_clk(unsigned char enable); 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun void init_clk_usdhc(u32 index); 41*4882a593Smuzhiyun void clock_init(void); 42*4882a593Smuzhiyun void hab_caam_clock_enable(unsigned char enable); 43*4882a593Smuzhiyun #endif 44