xref: /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/mx7d_rdc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:  GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __MX7D_RDC_H__
8*4882a593Smuzhiyun #define __MX7D_RDC_H__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun 	RDC_PER_GPIO1 = 0,
14*4882a593Smuzhiyun 	RDC_PER_GPIO2,
15*4882a593Smuzhiyun 	RDC_PER_GPIO3,
16*4882a593Smuzhiyun 	RDC_PER_GPIO4,
17*4882a593Smuzhiyun 	RDC_PER_GPIO5,
18*4882a593Smuzhiyun 	RDC_PER_GPIO6,
19*4882a593Smuzhiyun 	RDC_PER_GPIO7,
20*4882a593Smuzhiyun 	RDC_PER_IOMUXC_LPSR_GPR,
21*4882a593Smuzhiyun 	RDC_PER_WDOG1,
22*4882a593Smuzhiyun 	RDC_PER_WDOG2,
23*4882a593Smuzhiyun 	RDC_PER_WDOG3,
24*4882a593Smuzhiyun 	RDC_PER_WDOG4,
25*4882a593Smuzhiyun 	RDC_PER_IOMUXC_LPSR,
26*4882a593Smuzhiyun 	RDC_PER_GPT1,
27*4882a593Smuzhiyun 	RDC_PER_GPT2,
28*4882a593Smuzhiyun 	RDC_PER_GPT3,
29*4882a593Smuzhiyun 	RDC_PER_GPT4,
30*4882a593Smuzhiyun 	RDC_PER_ROMCP,
31*4882a593Smuzhiyun 	RDC_PER_KPP,
32*4882a593Smuzhiyun 	RDC_PER_IOMUXC,
33*4882a593Smuzhiyun 	RDC_PER_IOMUXCGPR,
34*4882a593Smuzhiyun 	RDC_PER_OCOTP,
35*4882a593Smuzhiyun 	RDC_PER_ANATOP_DIG,
36*4882a593Smuzhiyun 	RDC_PER_SNVS_HP,
37*4882a593Smuzhiyun 	RDC_PER_CCM,
38*4882a593Smuzhiyun 	RDC_PER_SRC,
39*4882a593Smuzhiyun 	RDC_PER_GPC,
40*4882a593Smuzhiyun 	RDC_PER_SEMA1,
41*4882a593Smuzhiyun 	RDC_PER_SEMA2,
42*4882a593Smuzhiyun 	RDC_PER_RDC,
43*4882a593Smuzhiyun 	RDC_PER_CSU,
44*4882a593Smuzhiyun 	RDC_PER_RESERVED1,
45*4882a593Smuzhiyun 	RDC_PER_RESERVED2,
46*4882a593Smuzhiyun 	RDC_PER_ADC1,
47*4882a593Smuzhiyun 	RDC_PER_ADC2,
48*4882a593Smuzhiyun 	RDC_PER_ECSPI4,
49*4882a593Smuzhiyun 	RDC_PER_FLEX_TIMER1,
50*4882a593Smuzhiyun 	RDC_PER_FLEX_TIMER2,
51*4882a593Smuzhiyun 	RDC_PER_PWM1,
52*4882a593Smuzhiyun 	RDC_PER_PWM2,
53*4882a593Smuzhiyun 	RDC_PER_PWM3,
54*4882a593Smuzhiyun 	RDC_PER_PWM4,
55*4882a593Smuzhiyun 	RDC_PER_SYSTEM_COUNTER_READ,
56*4882a593Smuzhiyun 	RDC_PER_SYSTEM_COUNTER_COMPARE,
57*4882a593Smuzhiyun 	RDC_PER_SYSTEM_COUNTER_CONTROL,
58*4882a593Smuzhiyun 	RDC_PER_PCIE_PHY,
59*4882a593Smuzhiyun 	RDC_PER_RESERVED3,
60*4882a593Smuzhiyun 	RDC_PER_EPDC,
61*4882a593Smuzhiyun 	RDC_PER_PXP,
62*4882a593Smuzhiyun 	RDC_PER_CSI,
63*4882a593Smuzhiyun 	RDC_PER_RESERVED4,
64*4882a593Smuzhiyun 	RDC_PER_LCDIF,
65*4882a593Smuzhiyun 	RDC_PER_RESERVED5,
66*4882a593Smuzhiyun 	RDC_PER_MIPI_CSI,
67*4882a593Smuzhiyun 	RDC_PER_MIPI_DSI,
68*4882a593Smuzhiyun 	RDC_PER_RESERVED6,
69*4882a593Smuzhiyun 	RDC_PER_TZASC,
70*4882a593Smuzhiyun 	RDC_PER_DDR_PHY,
71*4882a593Smuzhiyun 	RDC_PER_DDRC,
72*4882a593Smuzhiyun 	RDC_PER_RESERVED7,
73*4882a593Smuzhiyun 	RDC_PER_PERFMON1,
74*4882a593Smuzhiyun 	RDC_PER_PERFMON2,
75*4882a593Smuzhiyun 	RDC_PER_AXI_DEBUG_MON,
76*4882a593Smuzhiyun 	RDC_PER_QOSC,
77*4882a593Smuzhiyun 	RDC_PER_FLEXCAN1,
78*4882a593Smuzhiyun 	RDC_PER_FLEXCAN2,
79*4882a593Smuzhiyun 	RDC_PER_I2C1,
80*4882a593Smuzhiyun 	RDC_PER_I2C2,
81*4882a593Smuzhiyun 	RDC_PER_I2C3,
82*4882a593Smuzhiyun 	RDC_PER_I2C4,
83*4882a593Smuzhiyun 	RDC_PER_UART4,
84*4882a593Smuzhiyun 	RDC_PER_UART5,
85*4882a593Smuzhiyun 	RDC_PER_UART6,
86*4882a593Smuzhiyun 	RDC_PER_UART7,
87*4882a593Smuzhiyun 	RDC_PER_MU_A,
88*4882a593Smuzhiyun 	RDC_PER_MU_B,
89*4882a593Smuzhiyun 	RDC_PER_SEMAPHORE_HS,
90*4882a593Smuzhiyun 	RDC_PER_USB_PL301,
91*4882a593Smuzhiyun 	RDC_PER_RESERVED8,
92*4882a593Smuzhiyun 	RDC_PER_RESERVED9,
93*4882a593Smuzhiyun 	RDC_PER_RESERVED10,
94*4882a593Smuzhiyun 	RDC_PER_USB1,
95*4882a593Smuzhiyun 	RDC_PER_USB2,
96*4882a593Smuzhiyun 	RDC_PER_USB3,
97*4882a593Smuzhiyun 	RDC_PER_USDHC1,
98*4882a593Smuzhiyun 	RDC_PER_USDHC2,
99*4882a593Smuzhiyun 	RDC_PER_USDHC3,
100*4882a593Smuzhiyun 	RDC_PER_RESERVED11,
101*4882a593Smuzhiyun 	RDC_PER_RESERVED12,
102*4882a593Smuzhiyun 	RDC_PER_SIM1,
103*4882a593Smuzhiyun 	RDC_PER_SIM2,
104*4882a593Smuzhiyun 	RDC_PER_QSPI,
105*4882a593Smuzhiyun 	RDC_PER_WEIM,
106*4882a593Smuzhiyun 	RDC_PER_SDMA,
107*4882a593Smuzhiyun 	RDC_PER_ENET1,
108*4882a593Smuzhiyun 	RDC_PER_ENET2,
109*4882a593Smuzhiyun 	RDC_PER_RESERVED13,
110*4882a593Smuzhiyun 	RDC_PER_RESERVED14,
111*4882a593Smuzhiyun 	RDC_PER_ECSPI1,
112*4882a593Smuzhiyun 	RDC_PER_ECSPI2,
113*4882a593Smuzhiyun 	RDC_PER_ECSPI3,
114*4882a593Smuzhiyun 	RDC_PER_RESERVED15,
115*4882a593Smuzhiyun 	RDC_PER_UART1,
116*4882a593Smuzhiyun 	RDC_PER_UART2,
117*4882a593Smuzhiyun 	RDC_PER_UART3,
118*4882a593Smuzhiyun 	RDC_PER_RESERVED16,
119*4882a593Smuzhiyun 	RDC_PER_SAI1,
120*4882a593Smuzhiyun 	RDC_PER_SAI2,
121*4882a593Smuzhiyun 	RDC_PER_SAI3,
122*4882a593Smuzhiyun 	RDC_PER_RESERVED17,
123*4882a593Smuzhiyun 	RDC_PER_RESERVED18,
124*4882a593Smuzhiyun 	RDC_PER_SPBA,
125*4882a593Smuzhiyun 	RDC_PER_DAP,
126*4882a593Smuzhiyun 	RDC_PER_RESERVED19,
127*4882a593Smuzhiyun 	RDC_PER_RESERVED20,
128*4882a593Smuzhiyun 	RDC_PER_RESERVED21,
129*4882a593Smuzhiyun 	RDC_PER_CAAM,
130*4882a593Smuzhiyun 	RDC_PER_RESERVED22,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun enum {
134*4882a593Smuzhiyun 	RDC_MA_A7 = 0,
135*4882a593Smuzhiyun 	RDC_MA_M4,
136*4882a593Smuzhiyun 	RDC_MA_PCIE,
137*4882a593Smuzhiyun 	RDC_MA_CSI,
138*4882a593Smuzhiyun 	RDC_MA_EPDC,
139*4882a593Smuzhiyun 	RDC_MA_LCDIF,
140*4882a593Smuzhiyun 	RDC_MA_DISPLAY_PORT,
141*4882a593Smuzhiyun 	RDC_MA_PXP,
142*4882a593Smuzhiyun 	RDC_MA_CORESIGHT,
143*4882a593Smuzhiyun 	RDC_MA_DAP,
144*4882a593Smuzhiyun 	RDC_MA_CAAM,
145*4882a593Smuzhiyun 	RDC_MA_SDMA_PERI,
146*4882a593Smuzhiyun 	RDC_MA_SDMA_BURST,
147*4882a593Smuzhiyun 	RDC_MA_APBHDMA,
148*4882a593Smuzhiyun 	RDC_MA_RAWNAND,
149*4882a593Smuzhiyun 	RDC_MA_USDHC1,
150*4882a593Smuzhiyun 	RDC_MA_USDHC2,
151*4882a593Smuzhiyun 	RDC_MA_USDHC3,
152*4882a593Smuzhiyun 	RDC_MA_NC1,
153*4882a593Smuzhiyun 	RDC_MA_USB,
154*4882a593Smuzhiyun 	RDC_MA_NC2,
155*4882a593Smuzhiyun 	RDC_MA_TEST,
156*4882a593Smuzhiyun 	RDC_MA_ENET1_TX,
157*4882a593Smuzhiyun 	RDC_MA_ENET1_RX,
158*4882a593Smuzhiyun 	RDC_MA_ENET2_TX,
159*4882a593Smuzhiyun 	RDC_MA_ENET2_RX,
160*4882a593Smuzhiyun 	RDC_MA_SDMA,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #endif	/* __MX7D_RDC_H__*/
164