1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MX6UL_DDR_H__ 8*4882a593Smuzhiyun #define __ASM_ARCH_MX6UL_DDR_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef CONFIG_MX6UL 11*4882a593Smuzhiyun #error "wrong CPU" 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM0 0x020e0244 15*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM1 0x020e0248 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MX6_IOM_DRAM_RAS 0x020e024c 18*4882a593Smuzhiyun #define MX6_IOM_DRAM_CAS 0x020e0250 19*4882a593Smuzhiyun #define MX6_IOM_DRAM_CS0 0x020e0254 20*4882a593Smuzhiyun #define MX6_IOM_DRAM_CS1 0x020e0258 21*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDWE_B 0x020e025c 22*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT0 0x020e0260 23*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT1 0x020e0264 24*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA0 0x020e0268 25*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA1 0x020e026c 26*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA2 0x020e0270 27*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE0 0x020e0274 28*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE1 0x020e0278 29*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_0 0x020e027c 30*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS0 0x020e0280 31*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS1 0x020e0284 32*4882a593Smuzhiyun #define MX6_IOM_DRAM_RESET 0x020e0288 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MX6_IOM_GRP_ADDDS 0x020e0490 35*4882a593Smuzhiyun #define MX6_IOM_DDRMODE_CTL 0x020e0494 36*4882a593Smuzhiyun #define MX6_IOM_GRP_B0DS 0x020e0498 37*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRPK 0x020e049c 38*4882a593Smuzhiyun #define MX6_IOM_GRP_CTLDS 0x020e04a0 39*4882a593Smuzhiyun #define MX6_IOM_GRP_B1DS 0x020e04a4 40*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRHYS 0x020e04a8 41*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRPKE 0x020e04ac 42*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRMODE 0x020e04b0 43*4882a593Smuzhiyun #define MX6_IOM_GRP_DDR_TYPE 0x020e04b4 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /*__ASM_ARCH_MX6SX_DDR_H__ */ 46