xref: /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:  GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __MX6SX_RDC_H__
8*4882a593Smuzhiyun #define __MX6SX_RDC_H__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun 	RDC_PER_PWM1 = 0,
14*4882a593Smuzhiyun 	RDC_PER_PWM2,
15*4882a593Smuzhiyun 	RDC_PER_PWM3,
16*4882a593Smuzhiyun 	RDC_PER_PWM4,
17*4882a593Smuzhiyun 	RDC_PER_CAN1,
18*4882a593Smuzhiyun 	RDC_PER_CAN2,
19*4882a593Smuzhiyun 	RDC_PER_GPT,
20*4882a593Smuzhiyun 	RDC_PER_GPIO1,
21*4882a593Smuzhiyun 	RDC_PER_GPIO2,
22*4882a593Smuzhiyun 	RDC_PER_GPIO3,
23*4882a593Smuzhiyun 	RDC_PER_GPIO4,
24*4882a593Smuzhiyun 	RDC_PER_GPIO5,
25*4882a593Smuzhiyun 	RDC_PER_GPIO6,
26*4882a593Smuzhiyun 	RDC_PER_GPIO7,
27*4882a593Smuzhiyun 	RDC_PER_KPP,
28*4882a593Smuzhiyun 	RDC_PER_WDOG1,
29*4882a593Smuzhiyun 	RDC_PER_WODG2,
30*4882a593Smuzhiyun 	RDC_PER_CCM,
31*4882a593Smuzhiyun 	RDC_PER_ANATOPDIG,
32*4882a593Smuzhiyun 	RDC_PER_SNVSHP,
33*4882a593Smuzhiyun 	RDC_PER_EPIT1,
34*4882a593Smuzhiyun 	RDC_PER_EPIT2,
35*4882a593Smuzhiyun 	RDC_PER_SRC,
36*4882a593Smuzhiyun 	RDC_PER_GPC,
37*4882a593Smuzhiyun 	RDC_PER_IOMUXC,
38*4882a593Smuzhiyun 	RDC_PER_IOMUXCGPR,
39*4882a593Smuzhiyun 	RDC_PER_CANFD1,
40*4882a593Smuzhiyun 	RDC_PER_SDMA,
41*4882a593Smuzhiyun 	RDC_PER_CANFD2,
42*4882a593Smuzhiyun 	RDC_PER_SEMA1,
43*4882a593Smuzhiyun 	RDC_PER_SEMA2,
44*4882a593Smuzhiyun 	RDC_PER_RDC,
45*4882a593Smuzhiyun 	RDC_PER_AIPSTZ1_GE1,
46*4882a593Smuzhiyun 	RDC_PER_AIPSTZ2_GE2,
47*4882a593Smuzhiyun 	RDC_PER_USBO2H_PL301,
48*4882a593Smuzhiyun 	RDC_PER_USBO2H_USB,
49*4882a593Smuzhiyun 	RDC_PER_ENET1,
50*4882a593Smuzhiyun 	RDC_PER_MLB25,
51*4882a593Smuzhiyun 	RDC_PER_USDHC1,
52*4882a593Smuzhiyun 	RDC_PER_USDHC2,
53*4882a593Smuzhiyun 	RDC_PER_USDHC3,
54*4882a593Smuzhiyun 	RDC_PER_USDHC4,
55*4882a593Smuzhiyun 	RDC_PER_I2C1,
56*4882a593Smuzhiyun 	RDC_PER_I2C2,
57*4882a593Smuzhiyun 	RDC_PER_I2C3,
58*4882a593Smuzhiyun 	RDC_PER_ROMCP,
59*4882a593Smuzhiyun 	RDC_PER_MMDC,
60*4882a593Smuzhiyun 	RDC_PER_ENET2,
61*4882a593Smuzhiyun 	RDC_PER_EIM,
62*4882a593Smuzhiyun 	RDC_PER_OCOTP,
63*4882a593Smuzhiyun 	RDC_PER_CSU,
64*4882a593Smuzhiyun 	RDC_PER_PERFMON1,
65*4882a593Smuzhiyun 	RDC_PER_PERFMON2,
66*4882a593Smuzhiyun 	RDC_PER_AXIMON,
67*4882a593Smuzhiyun 	RDC_PER_TZASC1,
68*4882a593Smuzhiyun 	RDC_PER_SAI1,
69*4882a593Smuzhiyun 	RDC_PER_AUDMUX,
70*4882a593Smuzhiyun 	RDC_PER_SAI2,
71*4882a593Smuzhiyun 	RDC_PER_QSPI1,
72*4882a593Smuzhiyun 	RDC_PER_QSPI2,
73*4882a593Smuzhiyun 	RDC_PER_UART2,
74*4882a593Smuzhiyun 	RDC_PER_UART3,
75*4882a593Smuzhiyun 	RDC_PER_UART4,
76*4882a593Smuzhiyun 	RDC_PER_UART5,
77*4882a593Smuzhiyun 	RDC_PER_I2C4,
78*4882a593Smuzhiyun 	RDC_PER_QOSC,
79*4882a593Smuzhiyun 	RDC_PER_CAAM,
80*4882a593Smuzhiyun 	RDC_PER_DAP,
81*4882a593Smuzhiyun 	RDC_PER_ADC1,
82*4882a593Smuzhiyun 	RDC_PER_ADC2,
83*4882a593Smuzhiyun 	RDC_PER_WDOG3,
84*4882a593Smuzhiyun 	RDC_PER_ECSPI5,
85*4882a593Smuzhiyun 	RDC_PER_SEMA4,
86*4882a593Smuzhiyun 	RDC_PER_MUPORT1,
87*4882a593Smuzhiyun 	RDC_PER_CANFD_CPU,
88*4882a593Smuzhiyun 	RDC_PER_MUPORT2,
89*4882a593Smuzhiyun 	RDC_PER_UART6,
90*4882a593Smuzhiyun 	RDC_PER_PWM5,
91*4882a593Smuzhiyun 	RDC_PER_PWM6,
92*4882a593Smuzhiyun 	RDC_PER_PWM7,
93*4882a593Smuzhiyun 	RDC_PER_PWM8,
94*4882a593Smuzhiyun 	RDC_PER_AIPSTZ3_GE0,
95*4882a593Smuzhiyun 	RDC_PER_AIPSTZ3_GE1,
96*4882a593Smuzhiyun 	RDC_PER_RESERVED1,
97*4882a593Smuzhiyun 	RDC_PER_SPDIF,
98*4882a593Smuzhiyun 	RDC_PER_ECSPI1,
99*4882a593Smuzhiyun 	RDC_PER_ECSPI2,
100*4882a593Smuzhiyun 	RDC_PER_ECSPI3,
101*4882a593Smuzhiyun 	RDC_PER_ECSPI4,
102*4882a593Smuzhiyun 	RDC_PER_RESERVED2,
103*4882a593Smuzhiyun 	RDC_PER_RESERVED3,
104*4882a593Smuzhiyun 	RDC_PER_UART1,
105*4882a593Smuzhiyun 	RDC_PER_ESAI,
106*4882a593Smuzhiyun 	RDC_PER_SSI1,
107*4882a593Smuzhiyun 	RDC_PER_SSI2,
108*4882a593Smuzhiyun 	RDC_PER_SSI3,
109*4882a593Smuzhiyun 	RDC_PER_ASRC,
110*4882a593Smuzhiyun 	RDC_PER_RESERVED4,
111*4882a593Smuzhiyun 	RDC_PER_SPBA_MA,
112*4882a593Smuzhiyun 	RDC_PER_GIS,
113*4882a593Smuzhiyun 	RDC_PER_DCIC1,
114*4882a593Smuzhiyun 	RDC_PER_DCIC2,
115*4882a593Smuzhiyun 	RDC_PER_CSI1,
116*4882a593Smuzhiyun 	RDC_PER_PXP,
117*4882a593Smuzhiyun 	RDC_PER_CSI2,
118*4882a593Smuzhiyun 	RDC_PER_LCDIF1,
119*4882a593Smuzhiyun 	RDC_PER_LCDIF2,
120*4882a593Smuzhiyun 	RDC_PER_VADC,
121*4882a593Smuzhiyun 	RDC_PER_VDEC,
122*4882a593Smuzhiyun 	RDC_PER_SPBA_DISPLAYMIX,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun enum {
126*4882a593Smuzhiyun 	RDC_MA_A9_L2CACHE = 0,
127*4882a593Smuzhiyun 	RDC_MA_M4,
128*4882a593Smuzhiyun 	RDC_MA_GPU,
129*4882a593Smuzhiyun 	RDC_MA_CSI1,
130*4882a593Smuzhiyun 	RDC_MA_CSI2,
131*4882a593Smuzhiyun 	RDC_MA_LCDIF1,
132*4882a593Smuzhiyun 	RDC_MA_LCDIF2,
133*4882a593Smuzhiyun 	RDC_MA_PXP,
134*4882a593Smuzhiyun 	RDC_MA_PCIE_CTRL,
135*4882a593Smuzhiyun 	RDC_MA_DAP,
136*4882a593Smuzhiyun 	RDC_MA_CAAM,
137*4882a593Smuzhiyun 	RDC_MA_SDMA_PERI,
138*4882a593Smuzhiyun 	RDC_MA_SDMA_BURST,
139*4882a593Smuzhiyun 	RDC_MA_APBHDMA,
140*4882a593Smuzhiyun 	RDC_MA_RAWNAND,
141*4882a593Smuzhiyun 	RDC_MA_USDHC1,
142*4882a593Smuzhiyun 	RDC_MA_USDHC2,
143*4882a593Smuzhiyun 	RDC_MA_USDHC3,
144*4882a593Smuzhiyun 	RDC_MA_USDHC4,
145*4882a593Smuzhiyun 	RDC_MA_USB,
146*4882a593Smuzhiyun 	RDC_MA_MLB,
147*4882a593Smuzhiyun 	RDC_MA_TEST,
148*4882a593Smuzhiyun 	RDC_MA_ENET1_TX,
149*4882a593Smuzhiyun 	RDC_MA_ENET1_RX,
150*4882a593Smuzhiyun 	RDC_MA_ENET2_TX,
151*4882a593Smuzhiyun 	RDC_MA_ENET2_RX,
152*4882a593Smuzhiyun 	RDC_MA_SDMA,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #endif	/* __MX6SX_RDC_H__*/
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