1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MX6SX_DDR_H__ 8*4882a593Smuzhiyun #define __ASM_ARCH_MX6SX_DDR_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef CONFIG_MX6SX 11*4882a593Smuzhiyun #error "wrong CPU" 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM0 0x020e02ec 15*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM1 0x020e02f0 16*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM2 0x020e02f4 17*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM3 0x020e02f8 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MX6_IOM_DRAM_RAS 0x020e02fc 20*4882a593Smuzhiyun #define MX6_IOM_DRAM_CAS 0x020e0300 21*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT0 0x020e0310 22*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT1 0x020e0314 23*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA2 0x020e0320 24*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE0 0x020e0324 25*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE1 0x020e0328 26*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_0 0x020e032c 27*4882a593Smuzhiyun #define MX6_IOM_DRAM_RESET 0x020e0340 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS0 0x020e0330 30*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS1 0x020e0334 31*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS2 0x020e0338 32*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS3 0x020e033c 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MX6_IOM_GRP_ADDDS 0x020e05f4 35*4882a593Smuzhiyun #define MX6_IOM_DDRMODE_CTL 0x020e05f8 36*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRPKE 0x020e05fc 37*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRMODE 0x020e0608 38*4882a593Smuzhiyun #define MX6_IOM_GRP_B0DS 0x020e060c 39*4882a593Smuzhiyun #define MX6_IOM_GRP_B1DS 0x020e0610 40*4882a593Smuzhiyun #define MX6_IOM_GRP_CTLDS 0x020e0614 41*4882a593Smuzhiyun #define MX6_IOM_GRP_DDR_TYPE 0x020e0618 42*4882a593Smuzhiyun #define MX6_IOM_GRP_B2DS 0x020e061c 43*4882a593Smuzhiyun #define MX6_IOM_GRP_B3DS 0x020e0620 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /*__ASM_ARCH_MX6SX_DDR_H__ */ 46